Hardware Design
- How to Connect an ADC to an FPGA
- How to Design SPI Controller in VHDL
- How to Implement a Finite State Machine in VHDL
- How To Implement Shift-Register in VHDL Using a FIFO
- How to Implement a Digital Delay Using a Dual-Port RAM in VHDL
- What is a FIFO?
- How To Implement Clock Divider in VHDL
- How to Connect a Serial ADC to an FPGA
- How to implement a PWM in VHDL
- How to Implement a Programmable Timeout Counter
- How to Measure Pulse Duration Using VHDL
- How to design a good Edge Detector
- How to compute the frequency of a clock
- How to implement a Multi Port memory on FPGA
- How to implement an LFSR in VHDL
- How to implement a digital MUX in VHDL
- How to interface a FPGA processor with VHDL peripheral
- How to implement Galois multiplier in VHDL
- How to implement a Reed-Solomon Encoder in VHDL
- How to implement a shift register in VHDL
- How to implement a Parallel to Serial converter
- How to implement a Serial to Parallel converter
- SPI Slave VHDL design
Signal Processing
- How to Implement FIR Filter in VHDL
- How To Generate Sine Samples in VHDL
- How to Implement a Pipeline Multiplier in VHDL
- How to Implement NCO in VHDL
- How to Implement a sinusoidal DDS in VHDL
- Implement Digital ASK Modulator in VHDL
- Compute exp(x) in FPGA using VHDL
- How to Realize a FIR Test Bench in FPGA
- How to Quantize FIR Coefficient
- How to implement a digital filter without multiplier
- How to implement a convolutional interleaver
- How to implement convolutional encoder in VHDL
- How to implement moving average in VHDL
- How to compensate amplitude and phase imbalance in VHDL
- Multiplier optimization in VHDL
- CNN Kernel implementation in VHDL