What is a MUX?

When we implement a digital hardware architecture, we often need to select one input among several for our logic. This selection logic is called digital multiplexer or MUX.

The digital multiplexer is called “digital” to distinguish it from an analog multiplexer. An analog multiplexer implements the same function selecting the source of a signal from different analog sources instead of digital ones.

As is clear in Figure 1, a MUX can be visualized as an n-way virtual switch whose output can be connected to one of the different input sources. On the left side of Figure 1, you can see the typical MUX representation. The number near the input ports indicates the selector value used to route the selected input to the output port.

Figure-1 N-Way MUX

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VHDL implementation of a digital MUX

The digital MUX is one of the basic building blocks of a digital design. Using the VHDL we have basically two different ways to describe a digital MUX:

Concurrent description
Sequential description

Both the descriptions are totally equivalent and implement the same hardware logic. You can use concurrent or sequential depending on your coding style.

Below is a 4-way mux using a sequential VHDL description. The process is purely combinatorial: the sensitivity list includes all inputs (a1, a2, a3, a4, sel) and there is no clock.

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4 is
port(
  a1      : in  std_logic_vector(2 downto 0);
  a2      : in  std_logic_vector(2 downto 0);
  a3      : in  std_logic_vector(2 downto 0);
  a4      : in  std_logic_vector(2 downto 0);
  sel     : in  std_logic_vector(1 downto 0);
  b       : out std_logic_vector(2 downto 0));
end mux4;

architecture rtl of mux4 is
  -- declarative part: empty
begin

p_mux : process(a1,a2,a3,a4,sel)
begin
  case sel is
    when "00" => b <= a1 ;
    when "01" => b <= a2 ;
    when "10" => b <= a3 ;
    when others => b <= a4 ;
  end case;
end process p_mux;

end rtl;

MUX description using SEQUENTIAL VHDL statement

Below is a 4-way mux using a concurrent VHDL description with the SELECT statement

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4 is
port(
  a1      : in  std_logic_vector(2 downto 0);
  a2      : in  std_logic_vector(2 downto 0);
  a3      : in  std_logic_vector(2 downto 0);
  a4      : in  std_logic_vector(2 downto 0);
  sel     : in  std_logic_vector(1 downto 0);
  b       : out std_logic_vector(2 downto 0));
end mux4;

architecture rtl of mux4 is
  -- declarative part: empty
begin

  with sel select
    b <= a1 when "00",
       a2 when "01",
       a3 when "10",
       a4 when others;

end rtl;

MUX description using SELECT VHDL statement

Another VHDL description of a 4-way mux using a concurrent representation is given below

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4 is
port(
  a1      : in  std_logic_vector(2 downto 0);
  a2      : in  std_logic_vector(2 downto 0);
  a3      : in  std_logic_vector(2 downto 0);
  a4      : in  std_logic_vector(2 downto 0);
  sel     : in  std_logic_vector(1 downto 0);
  b       : out std_logic_vector(2 downto 0));
end mux4;

architecture rtl of mux4 is
  -- declarative part: empty
begin

  b <= a1 when (sel = "00") else
       a2 when (sel = "01") else
       a3 when (sel = "10") else
       a4;

end rtl;

MUX description using simple CONCURRENT VHDL statement

In Figure 2, Figure 3, Figure 4 are reported the implementations on a Cyclone IV FPGA of the sequential and concurrent implementations of the VHDL code reported above. As is clear, the circuit implementation is the same for both VHDL coding styles, even if the RTL view can be different.

Figure 2 – RTL and technology view for SELECT implementation of a 4-way MUX

Figure 3 – RTL and technology view for SEQUENTIAL implementation of a 4-way MUX

Figure 4 – RTL and technology view for a simple CONCURRENT implementation of a 4-way MUX

VHDL – MUX implementation using an array structure

If the number of MUX inputs is a power of two, we can take advantage of the VHDL syntax, implementing the MUX in a very compact VHDL description. The selector signal directly indexes the array, so the input count must match the selector range (e.g., 2-bit sel for 4 inputs).

To take advantage of the power-of-two number of inputs, we use the VHDL array structure.

In the VHDL code below, we define a user type that is an array of a signal using the same VHDL type of the MUX input.

The selector signal will be used as the index of the array.

The VHDL code is very compact and efficient as we can see below.

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity mux4 is
port(
  d0     : in  std_logic_vector(1 downto 0);
  d1     : in  std_logic_vector(1 downto 0);
  d2     : in  std_logic_vector(1 downto 0);
  d3     : in  std_logic_vector(1 downto 0);
  s      : in  std_logic_vector(1 downto 0);
  m      : out std_logic_vector(1 downto 0));
end mux4;

architecture rtl of mux4 is
type t_array_mux is array (0 to 3) of std_logic_vector(1 downto 0);
signal array_mux  : t_array_mux;

begin

  array_mux(0)  <= d0;
  array_mux(1)  <= d1;
  array_mux(2)  <= d2;
  array_mux(3)  <= d3;

  m <= array_mux(to_integer(unsigned(s)));

end rtl;

MUX description using simple ARRAY VHDL statement

Figure 5 reports the RTL and technology view of the MUX implementation using the array architecture implementation. As is clear, the final implementation is totally equivalent to the concurrent or sequential one.

Figure 5 – RTL and technology view array implementation of a 4-way MUX

MUX VHDL Simulation

Figure 6 shows the MUX implementation. The MUX outputs the corresponding input value depending on the selector signal

Figure 6 – VHDL simulation of a 4-way MUX

Conclusion

In this post, we covered different ways to implement digital MUX in VHDL:

VHDL Concurrent MUX implementation
VHDL Sequential MUX implementation
VHDL array based MUX implementation, when the input signals are a power of two

All the different VHDL descriptions are mapped into the same hardware.

References

[1] https://en.wikipedia.org/wiki/Multiplexer

[2] www.intel.com

[3] www.amd.com

[4] RTL HARDWARE DESIGN USING VHDL Coding for Efficiency, Portability, and Scalability – PONG P.CHU

How to implement a digital MUX in VHDL