How to compensate amplitude and phase imbalance in VHDL
Learn how to compensate I/Q amplitude and phase imbalance in VHDL with a complete pre-compensation implementation for quadrature modulators.
How to implement a shift register in VHDL
Learn four different ways to implement a shift register in VHDL: with signals, variables, for-loop, and a single-line description. Includes RTL views and Quartus examples.
How to implement moving average in VHDL
Learn how to implement a moving average filter in VHDL using an efficient pipeline-accumulator architecture.
How to implement convolutional encoder in VHDL
Learn how to implement a DVB-S convolutional encoder (rate 1/2, K=7) in VHDL. Includes architecture, VHDL code, simulation, and Matlab/Octave reference patterns.
How to implement a convolutional interleaver
Learn how to implement a convolutional interleaver in VHDL for DVB-S. Understand interleaving techniques to mitigate burst errors in digital communication channels.
How to implement a digital filter without multiplier
Implement an FIR filter in VHDL without multipliers using a LUT-based approach. Perfect for QPSK/ASK modulators with +/-1 inputs.
How to implement a Reed-Solomon Encoder in VHDL
Learn how to implement a Reed-Solomon encoder in VHDL using LFSR architecture, with step-by-step explanation and Matlab/Octave verification.
How to implement Galois multiplier in VHDL
VHDL implementation of a Galois field GF(2^m) multiplier with configurable polynomial. Includes step-by-step explanation of Galois arithmetic, simulation and layout results.
How to interface a FPGA processor with VHDL peripheral
Three architecture solutions for interfacing an FPGA processor with custom VHDL peripherals: dual-port memory, FIFO, and GPIO-like interfaces.