How to compute the frequency of a clock

Clock and digital design

When you use an FPGA you always need a clock. When you start the debug of your VHDL layout code on FPGA, often your design doesn’t work as it should!

It’ the hardware my friend!

Digital design has a big advantage w.r.t analog design:

if you implement a (good) synchronous design and simulate it, you are very confident that the design can work as it should.

But the reality is different!

I have a bad news when you start to debug your design on FPGA it always doesn’t work… Did it happen to you?

Figure1 – clock signal example
Figure1 – clock signal example

There is also a good news… (more…)

How to design a good Edge Detector

Level vs edge

In digital synchronous design sometimes we need to detect the transition ‘0’->’1′ or ‘1’->’0’ of a signal.

As a simple example, suppose you have a counter with enable input port connected to an external push button. You need to count +1 every time you push the button.

Figure1 – example of human generated pulse used to enable a counter
Figure1 – example of human generated pulse used to enable a counter

Let the counter clock to be for example 50 MHz. The clock period is 20 ns. Even if you are very very fast in pushing the button it will be difficult to generate a pulse of 20 ns in order to enable the counter for only one clock cycle.

For example, if you push the button even for few millisecond, let say for instance 200 ms, your counter will be enabled for 200 ms/20 ns = 10.000.000 of clock cycle!

As you can see we need another solution than trying to push the button very very fast! (more…)

How to measure pulse duration using VHDL

Classical Method

As you know, the classical method to measure a pulse characteristic is to use an oscilloscope. The oscilloscope can measure amplitude, width, frequency and many other pulse characteristics as in Figure1. Many times we do not have an oscilloscope or we don’t have the possibility to reach the signal we want to measure.

Figure1 – Pulse characteristics
Figure1 – Pulse characteristics

For example, if you want to measure a pulse inside your FPGA, it could be difficult. In this case, you don’t need to know the amplitude of the pulse: it is a digital signal that can get the values ‘0’ or ‘1’.


How to Implement a Programmable Timeout Counter

Control logic implementation

In this post, we want to implement a simple exercise in order to show how to implement a programmable time-out counter that uses three different input coding. It is an exercise in control logic that you can use in your FPGA/ASIC design.

The control logic is explained in Figure1:

Figure1 - Programmable Time-Out Counter Control logic
Figure1 – Programmable Time-Out Counter Control logic

we need to count three different type of events and the counting values can be programmable up to three different ways. For instance, starting with count 3 pulses from input 1 then 5 pulses from input 2 and then 7 pulses from input three. After that, the control logic shall generate a pulse. (more…)

How to Connect a Serial ADC to an FPGA

Connection of Serial ADC to FPGA

The ADC (Analog to Digital Converter) can be interfaced to FPGA/ASIC in a different way depending on the output interface. This post gives an overview on the different interfaces available in ADC interfacing. On modern ADC, when the sampling rate is below the 10 Msample/sec the ADCs often implement a serial interface to provides sampled data to the user. The serial interface is little bit complex w.r.t. a parallel interface but the use of serial protocol reduces the number of wires and allows interfacing the ADC to a microprocessor like Arduino or Rapsberry Pi.

In the serial interface, the serial clock provided by the device connected to the ADC is used also as ADC sampling clock.

Figure1 - Serial ADC connected to FPGA
Figure1 – Serial ADC connected to FPGA

In this post, we will see an example of how to interface the TI ADC128S022 used in the Altera DE0-nano Board (more…)

How To Implement Clock Divider in VHDL

Clock Design Overview

Often, inside our FPGA design, we have the necessity to generate a local clock from the system clock. With system clock, I mean the clock that is coming from an external board oscillator. Many modern FPGAs have the possibility to generate internal clocks, different from the external clocks, using internal PLL hard macro. So you can generate internal FPGA clock as multiple or sub-multiple of the external system clock.


Figure1 - FPGA with internal clock divider
Figure1 – FPGA with internal clock divider

Sometimes the PLL are used to modify the clock phase or to generate different clocks at the same frequency with different phase relationship. For instance, 3 clocks:


What is a FIFO?

Basic notion on FIFO (First-In First-Out)

FIFO means First-In First-Out. A FIFO is a structure used in hardware or software application when you need to buffer a data.
Basically, you can think about a FIFO as a bus queue in London.
The people that arrive first is the one who catch the bus first….

FIFO example at bus Stop
Figure1 – FIFO example at bus Stop

Of course, this example is valid only in London or in Japan, in other countries, it could be not be used 🙂 (more…)

How to Implement a Digital Delay Using a Dual Port Ram

Implement a Digital Delay Using a Dual Port Ram

The digital delay lines are one of the most used blocks in the digital design. When the digital delay is small in terms of numbers of Flip-Flop a simple shift register approach can be used. If the number of bits to delay i.e. the number of Flip-Flop utilized became important, a different approach should be used.

Digital Delay Implementation Architecture as Circular Buffer
Figure 1 – Digital Delay Implementation Architecture as Circular Buffer 

In this post, a FIFO delay approach has been presented. In that case, we used the FIFO macro provided by the FPGA vendor in order to implement a digital delay line.


How To Generate Sine Samples in VHDL

In Digital Signal Processing, often is required the implementation of transcendental math function as trigonometric functions (sine, cosine, tan, atan) or exponential and logarithmic functions and so on. An efficient way, when possible, is to implement an approximation of these functions using Look Up Table or LUT as the sine example in Figure1.

Figure1 - LUT implementing sine function
Figure1 – LUT implementing sine function


In modern FPGA a large amount of RAM/ROM memory is available, so the LUT implementation requires only FPGA memory hardware resources and few additive registers. (more…)