Clock and digital design
When you use an FPGA you always need a clock. When you start the debug of your VHDL layout code on FPGA, often your design doesn’t work as it should!
It’ the hardware my friend!
Digital design has a big advantage w.r.t analog design:
if you implement a (good) synchronous design and simulate it, you are very confident that the design can work as it should.
But the reality is different!
I have a bad news when you start to debug your design on FPGA it always doesn’t work… Did it happen to you?
There is also a good news… (more…)