How to Implement a sinusoidal DDS in VHDL

What is a sinusoidal Direct Digital Synthesis (DDS)?

The Direct Digital Synthesis (DDS) is a method of producing an analog waveform using a digital device. In this post, we are going to illustrate how to generate digitally a sine-wave using a digital device such as FPGA or ASIC.

Figure1 – DDS typical architecture

The sine/cosine wave generated can be used inside your digital design in order to perform digital up/down frequency conversion. (more…)

How to Implement NCO in VHDL

 What is an NCO?

An NCO is the acronym of Numerically Controlled Oscillator.

Figure 1 – NCO basic architecture

Basically, it is implemented with an accumulator which adds a constant value FCW (Frequency Control Word). The accumulator wrap around every time it reaches its maximum value. For example, if the maximum value is 15 (4-bit accumulator) and the FWC = 4, the accumulator will count: (more…)

How to Implement a Pipeline Multiplier in VHDL

Multiplier in modern FPGA

In the modern FPGA, the multiplication operation is implemented using a dedicated hardware resource. Such dedicated hardware resource generally implements 18×18 multiply and accumulate function that can be used for efficient implementation of complex DSP algorithms such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast fourier transform (FFT) for filtering and image processing applications etc.

The Multiplier-Accumulator blocks has a built-in multiplier and adder, which minimizes the fabric logic required to implement multiplication, multiply-add, and multiply-accumulate (MACC) functions. Implementation of these arithmetic functions results in efficient resource usage and improved performance for DSP applications. In addition to the basic MACC function, DSP algorithms typically need small amounts of RAM for coefficients and larger RAMs for data storage. (more…)

How to compute the frequency of a clock

Clock and digital design

When you use an FPGA you always need a clock. When you start the debug of your VHDL layout code on FPGA, often your design doesn’t work as it should!

It’ the hardware my friend!

Digital design has a big advantage w.r.t analog design:

if you implement a (good) synchronous design and simulate it, you are very confident that the design can work as it should.

But the reality is different!

I have a bad news when you start to debug your design on FPGA it always doesn’t work… Did it happen to you?

Figure1 – clock signal example
Figure1 – clock signal example

There is also a good news… (more…)

How to design a good Edge Detector

Level vs edge

In digital synchronous design sometimes we need to detect the transition ‘0’->’1′ or ‘1’->’0’ of a signal.

As a simple example, suppose you have a counter with enable input port connected to an external push button. You need to count +1 every time you push the button.

Figure1 – example of human generated pulse used to enable a counter
Figure1 – example of human generated pulse used to enable a counter

Let the counter clock to be for example 50 MHz. The clock period is 20 ns. Even if you are very very fast in pushing the button it will be difficult to generate a pulse of 20 ns in order to enable the counter for only one clock cycle.

For example, if you push the button even for few millisecond, let say for instance 200 ms, your counter will be enabled for 200 ms/20 ns = 10.000.000 of clock cycle!

As you can see we need another solution than trying to push the button very very fast! (more…)

How to Measure Pulse Duration Using VHDL

Classical Method

As you know, the classical method to measure a pulse characteristic is to use an oscilloscope. The oscilloscope can measure amplitude, width, frequency and many other pulse characteristics as in Figure1. Many times we do not have an oscilloscope or we don’t have the possibility to reach the signal we want to measure.

Figure1 – Pulse characteristics
Figure1 – Pulse characteristics

For example, if you want to measure a pulse inside your FPGA, it could be difficult. In this case, you don’t need to know the amplitude of the pulse: it is a digital signal that can get the values ‘0’ or ‘1’.

(more…)

How to Implement a Programmable Timeout Counter

Control logic implementation

In this post, we want to implement a simple exercise in order to show how to implement a programmable time-out counter that uses three different input coding. It is an exercise in control logic that you can use in your FPGA/ASIC design.

The control logic is explained in Figure1:

Figure1 - Programmable Time-Out Counter Control logic
Figure1 – Programmable Time-Out Counter Control logic

we need to count three different type of events and the counting values can be programmable up to three different ways. For instance, starting with count 3 pulses from input 1 then 5 pulses from input 2 and then 7 pulses from input three. After that, the control logic shall generate a pulse. (more…)

How to Connect a Serial ADC to an FPGA

Connection of Serial ADC to FPGA

The ADC (Analog to Digital Converter) can be interfaced to FPGA/ASIC in a different way depending on the output interface. This post gives an overview on the different interfaces available in ADC interfacing. On modern ADC, when the sampling rate is below the 10 Msample/sec the ADCs often implement a serial interface to provides sampled data to the user. The serial interface is little bit complex w.r.t. a parallel interface but the use of serial protocol reduces the number of wires and allows interfacing the ADC to a microprocessor like Arduino or Rapsberry Pi.

In the serial interface, the serial clock provided by the device connected to the ADC is used also as ADC sampling clock.

Figure1 - Serial ADC connected to FPGA
Figure1 – Serial ADC connected to FPGA

In this post, we will see an example of how to interface the TI ADC128S022 used in the Altera DE0-nano Board (more…)

How To Implement Clock Divider in VHDL

Clock Design Overview

Often, inside our FPGA design, we have the necessity to generate a local clock from the system clock. With system clock, I mean the clock that is coming from an external board oscillator. Many modern FPGAs have the possibility to generate internal clocks, different from the external clocks, using internal PLL hard macro. So you can generate internal FPGA clock as multiple or sub-multiple of the external system clock.

 

Figure1 - FPGA with internal clock divider
Figure1 – FPGA with internal clock divider

Sometimes the PLL are used to modify the clock phase or to generate different clocks at the same frequency with different phase relationship. For instance, 3 clocks:

(more…)