How to implement Galois multiplier in VHDL

Why Galois field

The Galois fields are mainly used in cryptography and error correction algorithm.

If you never deal with Galois field, at the beginning the topic could seem very hard to understand. In this post we want to address the galois field theory from the practical application point of view.

We will review:

  • the Galois arithmetic notation, just to understand how to interpret the equation
  • add/sum operation in Galois field
  • multiplier in Galois field
Figure 1 – Galois multiplier in GF(2^m)

the third point maybe is the most difficult to understand.

It might put noses out of joint after reading this post because I will not be very rigorous in the representation of the theory of the Galois fields. This post wishes to give you a practical implementation starting point for your VHDL design using Galois arithmetic.

I put a lot of references at the bottom of this post that will help you to go deeper in the Galois field theory if you are really interested in it.

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How to interface a FPGA processor with VHDL peripheral

FPGA and Processor

The modern FPGAs implement microprocessor internally either as soft-processor or hard-processor. The soft-processor is intended as microprocessor implemented into the FPGA starting from a VHDL/Verilog code.

So, in this case, the processor is synthesized using the current FPGA technology (and layout tool).

Soft-processors have the advantages to be portable into a different technology. LEON processor is a soft-processor example that is realized as a stand-alone chip and can be integrated into a VHDL design as IP.

Figure 1 – FPGA-SoC Processor to peripheral interface

The Hard-processor is intended as a dedicated FPGA silicon area that implements the processor.

As you can understand, it is dependent on the FPGA are you using. For example, Intel Cyclone V SoC family implements a dual-core processor ARM-Cortex A9.

Another example is the Xilinx ZYNQ that implement different processor families, ARM-Cortex A9, Arm Cortex-A53.

When we use a processor in FPGA (hard-processor or soft-processor) sometimes we need to interface such processor with our custom peripheral implemented in VHDL (or Verilog or other custom implementation). In this case, we could experience different issues in the processor – peripheral interfacing:

  • A bus of different size
  • Different interface signals
  • Synchronization during READ/WRITE operation

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How to implement a digital MUX in VHDL

What is a MUX?

When we implement a digital hardware architecture, we often need to select an input to our logic between several different inputs. This selection logic is called digital multiplexer or MUX.

We name it digital multiplexer, to distinguish it from an analog multiplexer. An analog multiplexer implements the same function as digital MUX selecting the source of a signal from different analog source instead of digital.

As clear in Figure1, a MUX can be visualized as an n-way virtual switch whose output can be connected to one of the different input sources. On the left side of the Figure1, you can see the typical MUX representation. The number near the input ports indicates the selector value used to route the selected input to the output port.

Figure-1 N-Way MUX

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How to implement an LFSR in VHDL

What is an LFSR

A linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. We can use this type of functions in many application such as counters, crypto, ber-meter, CRC generation, scrambling/descrambling algorithm, test application and so on

An LFSR of length N can generate 2^N-1 different states where the values look like pseudo-random values.

There are two different types of LFSR implementation the FIBONACCI and the GALOIS implementation as in Figure1. The LFSR implementations are equivalent.

Figure 1 – LSFR generic architecture

 

If we are implementing the LFSR in hardware, the Galois implementation is much more efficient since use two input XOR function and the XOR function is implemented between two consecutive registers. Read More

How to Implement Division in VHDL

VHDL integer division should be really avoided?

In VHDL there are the math primitive subtraction, addiction, and multiplication that are generally available in the libraries provided by the FPGA or ASIC vendor.

For example, in this post, we saw how to implement a pipelined multiplier. The example shows the use of multiplication and addition primitives.

The division is a bit more complex case. Generally, the deployment of the division requires a much more complex logic circuit, and for this reason, we tend to avoid, where possible, the use of the division operator unless there are special cases.

Figure 1 – division of two floating-point numbers

If we have to divide by 2 or power of two, the implementation is simply shifting to the right of the number to divide.

In binary representation, shifting to the right of a position corresponds to a division by two, as in a decimal representation a shifting to the right corresponds to a division by 10.

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How to Quantize FIR Coefficient

Fixed vs floating point representation

When we use FPGA, we need to deal with fixed-point arithmetic. Even if new FPGA like Intel Stratix 10 implements floating-point multiplier, if we need to implement Digital Signal Processing (DSP) in FPGA we have to use fixed-point arithmetic.

Many people have serious problems dealing with fixed-point binary representation or quantization of floating point value in fixed-point.

Figure 1 – Floating-point vs Quantized FIR impulse response

In this post, I explained how to divide a number for a constant in VHDL. Of course, you need to have the basic of binary number representation that you can find in this post.

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VHDL Array

What is an array

In any software programming language, when we need to deal with a collection of elements of the same type we can take advantage of the dedicated data structures provided by the language. In VHDL such kind of structure is defined “array“.

We can collect any data type object in an array type, many of the predefined VHDL data types are defined as an array of a basic data type.

An example is:

type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;
Figure 1 – example of VHDL array definition and addressing

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VHDL FOR-LOOP statement

VHDL Iterative Statement

In VHDL the FOR-LOOP statement is a sequential statement that can be used inside a process statement as well as in subprograms.

The FOR-LOOP statement is used whenever an operation needs to be repeated.

In VHDL behavioral code, i.e. when we write a VHDL code of a test bench in a pure behavioral model, the FOR-LOOP usage statement can be considered as a common SW implementation of a loop statement as in the other SW languages.

In VHDL RTL the FOR-LOOP statement shall be used taking into account the final hardware implementation.

This consideration, of course, is always valid in any VHDL code implementation.

The FOR-LOOP statement is more difficult to visualize as a final result in HW implementation. Read More

VHDL CASE statement

VHDL multiple conditional statement

In this post, we have introduced the conditional statement. The IF-THEN-ELSE is a VHDL statement that allows implementing a choice between different options. When the number of options greater than two we can use the VHDL “ELSIF” clause.  In case of multiple options, VHDL provides a more powerful statement both in the concurrent and sequential version:

  • CASE-WHEN sequential statement
  • WITH-SELECT concurrent statement
Figure 1 – Multiple conditional statement visual representation

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IF-THEN-ELSE statement in VHDL

VHDL Conditional Statement

VHDL is a Hardware Description Language that is used to describe at a high level of abstraction a digital circuit in an FPGA or ASIC.

When we need to perform a choice or selection between two or more choices, we can use the VHDL conditional statement.

Since the VHDL is a concurrent language, it provides two different solutions to implement a conditional statement:

  • sequential conditional statement
  • concurrent conditional statement
Figure 1 – Typical conditional statement representation

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