Vivado is the Hardware Development suite used to create a VHDL, Verilog, or any other HDL design on the latest Xilinx FPGA. In other words, when you need to translate your VHDL design into a configuration file to be downloaded into a Xilinx FPGA, you need Vivado framework.

Vivado is an integrated tool that allows you to perform the complete design flow for a Xilinx FPGA:

• Simulate
• Synthesize
• Map
• Route
• Analyze Timing
• Create a bit-stream FPGA configuration File
• Configure FPGA
• Debug the FPGA using ILA (Integrated Logic Analyzer)

In this post, we are going to see how to initialize Vivado tool to be ready to create an FPGA bit-stream programming file, starting from a simple VHDL code.

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In this post, we are going to design the VHDL code for the SPI slave module that can be connected to an SPI master.

You will see:

• SPI slave typical protocol
• SPI slave four wire hardware design
• VHDL implementation of a 4-wire SPI slave
• VHDL simulation of SPI Master-slave communication
• Layout consideration for SPI slave implementation

Serial Peripheral Interface Introduction – SPI Master / Slave

In a previous post, we introduced the SPI master controller module. The SPI master originates the frame for reading and writing multiple SPI slave devices using individual slave select (SS) lines.

The SPI is a three or four-wire serial bus as you can see in Figure 1

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VHDL can implement procedures. Even if the VHDL is a hardware description language, it can define procedures like a common programming language.

When we use a procedure, we always need to take in mind how the procedure code is translated in hardware implementation.

In this post, we will address the classical use of a procedure. It is a software approach, not a hardware approach.

First of all, as a golden rule, we need to take in mind what my professor of computer science used to repeat to me during the lessons at university:

When you need to write twice a piece of code, write a procedure or function.

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IEEE Computer Society in collaboration with the IEEE Education Society (South East Michigan Chapters) is offering TWO half-day workshops on Embedded Systems on Saturday, October 17th & 24th, 2020.

This workshop is open to all industry professionals, both experienced and newly minted engineers, as well as students. This is the 18th year that the event is being held.

The aim is to disseminate knowledge, directly benefitting the IEEE members, at the same time improve the technology skills pool, indirectly boosting the Michigan economy.

Speakers and experts from the embedded systems industry will be making presentations, and will also be available for discussions and networking throughout the day. In addition to the technical presentations, there will be industry information display and professional recruitment sessions. Use this opportunity for virtual networking with other engineers, industry experts, and embedded enthusiasts.

I’ll partecipate on October 24th talking about:

“The role of VHDL in embedded systems the advantages of a Hardware Description Language“

here the link to the conference: https://bit.ly/embed2020

In the last years, Machine Learning (ML), Artificial Intelligence (AI), Deep Learning are topics that are driving electronic device development.

ML and AI are starving in computational power.

The FPGA, mainly the modern FPGAs, are used in ML/AI since they can implement a lot of convolutional engines inside due to the intrinsic parallel architecture. 

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When FPGAs do not implement a multiplier HW macro

The modern FPGAs implement multiplication using a dedicated hardware resource. Such dedicated hardware resource generally implements 18×18 multiply and accumulate function. Many FPGAs use two 9×9 multiplier IP to implement a single 18×18 multiplier macro. It depends on the technology you are using.

Depending on the technology and FPGA you are using it is also possible to have no multiplier at all as dedicated IP. In this case, if you need to perform a multiplication it could be a problem. Multiplication is a very demanding operator in term of area and timing resources, so you need to pay attention to the operand number of bits in order to minimize the area and timing impact on your FPGA.

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Parallelize after serializing

In this post, we analyzed the VHDL code for a parallel to serial converter. This approach is very useful in interfacing different devices. Many FPGA vendors like Xilinx, Intel/Altera give us the possibility to use internal serializer-deserializer such as a serial transceiver. In this post, we want to implement the complementary interface of the parallel to serial interface. We will see how to implement the VHDL code for a serial to parallel interface in order to get back the parallel data bus we sent in the transmitter device. In other words, we will implement the VHDL block in the of the bottom right of Figure1

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Connecting two devices

When we need to transfer data from two different devices, the simple way is to use the minimum numbers of wires. For instance, if we need to transfer a data bus of 16 bits between two different FPGA at a rate of 1 MHz, we need to connect at least

16-bit data + 1 bit enable + 1 bit clock = 18 wires running @ 1 MHz. As you can see, these are a lot of wires! Moreover, a skew between the bits in the parallel data bus can affect the connection integrity.

Another method for data transfer, could be to serialize the parallel data using less connection.

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The real mixing refers to the translation of a signal in frequency by multiplying it with a single oscillator signal as in figure below

This approach is performed using the I/Q modulator technique. The I/Q modulator is a critical component in the signal chain for modern digital transmitters. An I/Q modulators perform the frequency translation that mixes the baseband signal to the desired location in the RF spectrum. An I/Q modulator consists of a local oscillator (LO) input that is split into in-phase (I) and quadrature (Q) components that are separated by 90°. An example of I/Q modulator is given in [3] These two signals drive separate mixers that are also driven by I and Q baseband signals processor.

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