CNN Kernel implementation in VHDL
Learn how to implement a CNN convolution kernel in VHDL for FPGA. Understand INT8 quantization, FIR filter analogy, and bit-width management for efficient inference.
Signal Processing
Multiplier optimization in VHDL
Learn how to optimize VHDL multipliers when one operand is near its maximum value. A practical guide using sine/cosine quantization with ±10° range.
How to compensate amplitude and phase imbalance in VHDL
Learn how to compensate I/Q amplitude and phase imbalance in VHDL with a complete pre-compensation implementation for quadrature modulators.
How to implement moving average in VHDL
Learn how to implement a moving average filter in VHDL using an efficient pipeline-accumulator architecture.
How to implement convolutional encoder in VHDL
Learn how to implement a DVB-S convolutional encoder (rate 1/2, K=7) in VHDL. Includes architecture, VHDL code, simulation, and Matlab/Octave reference patterns.
How to implement a convolutional interleaver
Learn how to implement a convolutional interleaver in VHDL for DVB-S. Understand interleaving techniques to mitigate burst errors in digital communication channels.
How to implement a digital filter without multiplier
Implement an FIR filter in VHDL without multipliers using a LUT-based approach. Perfect for QPSK/ASK modulators with +/-1 inputs.
How to Quantize FIR Coefficient
Learn how to quantize FIR filter coefficients from floating-point to fixed-point representation using MATLAB or Scilab. Step-by-step guide with code example.
How to Realize a FIR Test Bench in FPGA
Build an FIR test bench on FPGA in VHDL with a data generator, output buffer, and interactive simulation of impulse and step response.