Skip to content
SURF-VHDL
  • VHDL
  • Design
  • Tools
  • About Us
    • Privacy Policy
    • Cookie Policy
  • Courses

Signal Processing

Compute exp(x) in FPGA using VHDL

Learn how to implement the exponential function exp(x) in FPGA using VHDL with a LUT-based approach. Includes fixed-point quantization, Matlab code, and complete VHDL example.

Categories Signal Processing Tags Signal Processing
March 15, 2017 Updated October 7, 2026 By SURF VHDL

Implement Digital ASK Modulator in VHDL

Learn how ASK modulation works and implement a digital ASK modulator in VHDL for FPGA. Complete code for mapper, up-converter, and layout on Cyclone III.

Categories Signal Processing Tags Signal Processing
March 7, 2017 Updated October 7, 2026 By SURF VHDL

How to Implement a sinusoidal DDS in VHDL

Generate a sinusoidal signal in FPGA with this VHDL DDS implementation featuring NCO and look-up table for phase-to-amplitude conversion.

Categories Signal Processing Tags Signal Processing
February 17, 2017 Updated October 7, 2026 By SURF VHDL

How to Implement NCO in VHDL

Learn how to implement a Numerically Controlled Oscillator (NCO) in VHDL for FPGA. Complete guide with accumulator theory, fixed-point math, and synthesizable RTL code.

Categories Signal Processing Tags Signal Processing
February 3, 2017 Updated October 7, 2026 By SURF VHDL

How to Implement a Pipeline Multiplier in VHDL

Learn how to implement a pipelined multiplier in VHDL. Covers signed multiplication, partial product decomposition, and pipeline architecture for FPGAs.

Categories Signal Processing Tags Signal Processing
December 29, 2016 Updated October 7, 2026 By SURF VHDL

How To Generate Sine Samples in VHDL

Learn how to generate sine wave samples for a Look-Up Table (LUT) in VHDL. Covers quantization, VHDL testbench code, and ROM implementation.

Categories Signal Processing Tags Signal Processing
March 1, 2016 Updated October 7, 2026 By SURF VHDL

How to Implement FIR Filter in VHDL

Learn how to implement a 4-tap FIR filter in VHDL with fully pipelined architecture, 8-bit signed inputs and coefficients.

Categories Signal Processing Tags Signal Processing
November 15, 2015 Updated October 7, 2026 By SURF VHDL
Newer posts
← Previous Page1 Page2
© 2015 – 2026 SURF-VHDL • Built with GeneratePress Privacy Policy • Cookie Policy

Cookie Policy

We use cookies to improve your user experience and analyze website traffic. By clicking "Accept", you consent to the use of cookies. Read our Privacy Policy.

Search