TCL script Vivado Project Tutorial

December 27, 2021December 27, 2021 Surf-VHDL 2 Comments

Vivado is the Hardware Development suite used to implement a design in Xilinx FPGA. In this post, is reported how to create a Vivado project using the Graphical User Interface (GUI). This is the fastest and common approach to creating a project in Vivado.

Vivado GUI performs the complete design flow for a Xilinx FPGA:

Simulate
Synthesize
Map
Route
Analyze Timing
Create a bit-stream FPGA configuration File
Configure FPGA
Debug the FPGA using ILA (Integrated Logic Analyzer)

Vivado also allows the user to perform the design flow using TCL language.

The TCL scripting is very useful to create a compact and deterministic way to realize a layout flow in FPGA. This approach is adopted by expert users. You should take it into consideration even if you are not an expert. In this post, we are going to see a simple example that can be used as a template for the Vivado TCL project script. The project created using the TCL script can be also opened and edited using the Vivado GUI. All the analysis as timing, area, etc can be performed using GUI after design flow completion.

How to implement a digital MUX in VHDL

June 23, 2018September 20, 2020 Surf-VHDL 2 Comments

Before reading the post, if you need the VHDL code example of the Digital MUX, just put your email in the box you find in the post. There is no need to post a comment asking me for the code 🙂
If you don’t receive the email, please check your SPAM folder, enjoy!

What is a MUX?

When we implement a digital hardware architecture, we often need to select an input to our logic between several different inputs. This selection logic is called digital multiplexer or MUX.

We name it digital multiplexer, to distinguish it from an analog multiplexer. An analog multiplexer implements the same function as digital MUX selecting the source of a signal from different analog source instead of digital.

As clear in Figure1, a MUX can be visualized as an n-way virtual switch whose output can be connected to one of the different input sources. On the left side of the Figure1, you can see the typical MUX representation. The number near the input ports indicates the selector value used to route the selected input to the output port.

What is a FIFO?

April 23, 2016October 7, 2017 Surf-VHDL 13 Comments

Basic notion on FIFO (First-In First-Out)

FIFO means First-In First-Out. A FIFO is a structure used in hardware or software application when you need to buffer a data.
Basically, you can think about a FIFO as a bus queue in London.
The people that arrive first is the one who catch the bus first….

Of course, this example is valid only in London or in Japan, in other countries, it could be not be used 🙂 Read More