Surf-VHDL https://surf-vhdl.com/ The Easiest Way To Learn VHDL Mon, 27 Dec 2021 09:50:34 +0000 en-US hourly 1 https://wordpress.org/?v=6.5.2 https://surf-vhdl.com/wp/wp-content/uploads/2016/11/cropped-SURFVHDL_400x400-32x32.jpg Surf-VHDL https://surf-vhdl.com/ 32 32 TCL script Vivado Project Tutorial https://surf-vhdl.com/tcl-script-vivado-project-tutorial/ https://surf-vhdl.com/tcl-script-vivado-project-tutorial/#comments Mon, 27 Dec 2021 09:46:29 +0000 https://surf-vhdl.com/?p=2097 Vivado is the Hardware Development suite used to implement a design in Xilinx FPGA. In this post, is reported how to create a Vivado project using the Graphical User Interface (GUI). This is the fastest and common approach to creating a project in Vivado. Vivado GUI performs the complete design flow for a Xilinx FPGA: […]

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]]> https://surf-vhdl.com/tcl-script-vivado-project-tutorial/feed/ 2 Vivado Project Tutorial https://surf-vhdl.com/vivado-project-tutorial/ https://surf-vhdl.com/vivado-project-tutorial/#comments Fri, 24 Dec 2021 12:09:38 +0000 https://surf-vhdl.com/?p=2079 Vivado is the Hardware Development suite used to create a VHDL, Verilog, or any other HDL design on the latest Xilinx FPGA. In other words, when you need to translate your VHDL design into a configuration file to be downloaded into a Xilinx FPGA, you need Vivado framework. Vivado is an integrated tool that allows […]

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]]> https://surf-vhdl.com/vivado-project-tutorial/feed/ 1 SPI Slave VHDL design https://surf-vhdl.com/spi-slave-vhdl-design/ https://surf-vhdl.com/spi-slave-vhdl-design/#respond Thu, 18 Nov 2021 18:39:57 +0000 https://surf-vhdl.com/?p=2053 In this post, we are going to design the VHDL code for the SPI slave module that can be connected to an SPI master. You will see: SPI slave typical protocol SPI slave four wire hardware design VHDL implementation of a 4-wire SPI slave VHDL simulation of SPI Master-slave communication Layout consideration for SPI slave […]

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]]> https://surf-vhdl.com/spi-slave-vhdl-design/feed/ 0 How to Declare a Procedure in VHDL https://surf-vhdl.com/how-to-declare-a-procedure-in-vhdl/ https://surf-vhdl.com/how-to-declare-a-procedure-in-vhdl/#respond Sat, 26 Dec 2020 12:07:23 +0000 https://surf-vhdl.com/?p=2040 VHDL can implement procedures. Even if the VHDL is a hardware description language, it can define procedures like a common programming language. When we use a procedure, we always need to take in mind how the procedure code is translated in hardware implementation. In this post, we will address the classical use of a procedure. […]

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]]> https://surf-vhdl.com/how-to-declare-a-procedure-in-vhdl/feed/ 0 18th Annual Embedded Systems Workshop https://surf-vhdl.com/18th-annual-embedded-systems-workshop/ https://surf-vhdl.com/18th-annual-embedded-systems-workshop/#respond Sun, 11 Oct 2020 20:13:36 +0000 https://surf-vhdl.com/?p=2032 IEEE Computer Society in collaboration with the IEEE Education Society (South East Michigan Chapters) is offering TWO half-day workshops on Embedded Systems on Saturday, October 17th & 24th, 2020. This workshop is open to all industry professionals, both experienced and newly minted engineers, as well as students. This is the 18th year that the event […]

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]]> https://surf-vhdl.com/18th-annual-embedded-systems-workshop/feed/ 0 CNN Kernel implementation in VHDL https://surf-vhdl.com/cnn-kernel-implementation-in-vhdl/ https://surf-vhdl.com/cnn-kernel-implementation-in-vhdl/#respond Sun, 26 Apr 2020 16:14:00 +0000 https://surf-vhdl.com/?p=1999 In the last years, Machine Learning (ML), Artificial Intelligence (AI), Deep Learning are topics that are driving electronic device development. ML and AI are starving in computational power. The FPGA, mainly the modern FPGAs, are used in ML/AI since they can implement a lot of convolutional engines inside due to the intrinsic parallel architecture.  The […]

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]]> https://surf-vhdl.com/cnn-kernel-implementation-in-vhdl/feed/ 0 Multiplier optimization in VHDL https://surf-vhdl.com/multiplier-optimization-in-vhdl/ https://surf-vhdl.com/multiplier-optimization-in-vhdl/#respond Tue, 23 Apr 2019 16:39:30 +0000 https://surf-vhdl.com/?p=1930 When FPGAs do not implement a multiplier HW macro The modern FPGAs implement multiplication using a dedicated hardware resource. Such dedicated hardware resource generally implements 18×18 multiply and accumulate function. Many FPGAs use two 9×9 multiplier IP to implement a single 18×18 multiplier macro. It depends on the technology you are using. Depending on the […]

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]]> https://surf-vhdl.com/multiplier-optimization-in-vhdl/feed/ 0 How to implement a Serial to Parallel converter https://surf-vhdl.com/how-to-implement-a-serial-to-parallel-converter/ https://surf-vhdl.com/how-to-implement-a-serial-to-parallel-converter/#comments Sun, 07 Apr 2019 13:37:13 +0000 https://surf-vhdl.com/?p=1914 Parallelize after serializing In this post, we analyzed the VHDL code for a parallel to serial converter. This approach is very useful in interfacing different devices. Many FPGA vendors like Xilinx, Intel/Altera give us the possibility to use internal serializer-deserializer such as a serial transceiver. In this post, we want to implement the complementary interface […]

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]]> https://surf-vhdl.com/how-to-implement-a-serial-to-parallel-converter/feed/ 1 How to implement a Parallel to Serial converter https://surf-vhdl.com/how-to-implement-a-parallel-to-serial-converter/ https://surf-vhdl.com/how-to-implement-a-parallel-to-serial-converter/#comments Sun, 31 Mar 2019 20:05:01 +0000 https://surf-vhdl.com/?p=1902 Connecting two devices When we need to transfer data from two different devices, the simple way is to use the minimum numbers of wires. For instance, if we need to transfer a data bus of 16 bits between two different FPGA at a rate of 1 MHz, we need to connect at least 16-bit data […]

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]]> https://surf-vhdl.com/how-to-implement-a-parallel-to-serial-converter/feed/ 2 How to compensate amplitude and phase imbalance in VHDL https://surf-vhdl.com/how-to-compensate-amplitude-and-phase-imbalance-in-vhdl/ https://surf-vhdl.com/how-to-compensate-amplitude-and-phase-imbalance-in-vhdl/#comments Mon, 04 Mar 2019 21:25:27 +0000 https://surf-vhdl.com/?p=1876 The real mixing refers to the translation of a signal in frequency by multiplying it with a single oscillator signal as in figure below This approach is performed using the I/Q modulator technique. The I/Q modulator is a critical component in the signal chain for modern digital transmitters. An I/Q modulators perform the frequency translation […]

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