Finite Impulse Response (FIR) filters are characterized by a time response depending only on a given number of the last samples of the input signal. For a causal discrete-time FIR filter of order N, each value of the output sequence is a weighted sum of the most recent input values:

where:

x[n] is the input signal,

y[n] is the output signal,

N is the filter order; a Nth-order filter has (N+1) terms on the right-hand side

bi is the value of the impulse response at the i’th instant for 0<= i<=N of a Nth-order FIR filter. If the filter is a direct form FIR filter then is also a coefficient of the filter (see Figure1).

The ADC converters translate analog electrical signals, usually the voltage amplitude, into a sequence of discrete values (integer number) for data processing purposes. The bit resolution of the analog to digital conversion determines the magnitude of the quantization error. The number of discrete levels depends on the number of ADC bit resolution. For an N-bit ADC, the number of discrete possible values is 2^N.

For example, for 8-bit ADC the input signal is discretized in 2^8=256 different values.

In this post, we want to give an overview to binary number representation for negative numbers. Will be review three different representations for the negative number.

To understand binary numbers, we can start recalling elementary school math.

When we first learned about numbers in the decimal system, the number where organized into columns:

H | T | O 4 | 3 | 2

such that

“H” is the hundreds column,

“T” is the tens column,

“O” is the ones column.

So the number “432” is 4-hundreds plus 3-tens plus 2-ones. Read More

Probably you will be asked, “Why should I learn VHDL?” If you are involved in Electronic Hardware design using FPGA or ASIC, you’ll definitely hear of the high-level compilers/synthesizer. Now certainly, you may be thinking:

“I’m really a lucky person because the current technology is helping me in designing FPGA or ASIC hardware without the need to learn all about that hardware”.

The question is: can I use High-level synthesizer to exploit the ability of the software to develop different projects? The answer is probably yes, but with some limitation. Think about this issue: if you need to call a guy to develop a project, who you would you trust?

Who improvise himself/herself hardware designer?

A person who deeply understands the problems of the system?

The high-level synthesizers have made more democratic access to the FPGA hardware development, but keeping away the designer from the physical device, away from the silicon implementation.

Although, on one hand, using high-level synthesizers the design can be developed very fast, on the other side there is the risk of not having control of what you are doing.

If you need a professional service, you want to be sure that the person you hired have the mastery of what he/she is doing.

When the going gets tough, the tough get going.

The VHDL is a Hardware Description Language that allows the designer to model the hardware circuit with maximum flexibility and relatively easily. Doing so, however, it requires that you also have the knowledge of what are you doing. Another powerful Hardware Description Language is Verilog.

Most often this type of languages are confused and mistakenly associated to a purely software language.

This is due to the fact that it is difficult to make clear the distinction between software programming language and hardware description language.

The VHDL is a language that is used to describe a hardware project with enough level of abstraction, but in the same time, with a complete control of the hardware model.

With VHDL you can translate high-level design description into logic gates inside the silicon. If we start from this principle you can better understand how to use this powerful tool.

Few days ago, Intel announced they want to acquire ALTERA, one of the biggest FPGA providers. Such fusion can pave the way toward a new era of microprocessors with embedded FPGA used as a custom and re-configurable co-processor.

It could be a new page in the use of such devices by opening the opportunity to the hardware designers to develop new projects on innovative platforms.

The knowledge of VHDL in this field becomes certainly a must.

What do you answer to the initial question?

We appreciate any of your comment, please post below:

Modelsim is one of the best multi-language HDL simulator developed by Mentor Graphics.

Modelsim is essential for simulation of hardware description languages such as VHDL, Verilog and SystemC. Modelsim includes also a powerful C debugger.

ModelSim can be used independently, or in conjunction with Altera Quartus or Xilinx ISE/Vivado. The HDL simulation can be performed either using the graphical user interface (GUI), or automatically using TCL/TK scripts.

Modelsim runs under FlexLm license and, as you can imagine, a single license is quite expensive for an end user such as a student or hobbyist.

There are two opportunities to get a legal free Modelsim license:

If you are a student, you can get a free student edition at Mentor website link

From Altera website, downloading Quartus II web edition. Altera provides a free license limited to Altera FPGA. This means you cannot compile technology libraries of ASIC or FPGA such as Xilinx, Microsemi but you can compile and simulate you own RTL code.