## What is an LFSR

A linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. We can use this type of functions in many application such as counters, crypto, ber-meter, CRC generation, scrambling/descrambling algorithm, test application and so on

An LFSR of length N can generate 2^N-1 different states where the values look like pseudo-random values.

There are two different types of LFSR implementation the FIBONACCI and the GALOIS implementation as in Figure1. The LFSR implementations are equivalent.

If we are implementing the LFSR in hardware, the Galois implementation is much more efficient since use two input XOR function and the XOR function is implemented between two consecutive registers. Read More

## VHDL integer division should be really avoided?

In VHDL there are the primitive math subtraction, addiction, and multiplication that are generally available in the libraries provided by the FPGA or ASIC vendor.

For example, in this post, we saw how to implement a pipelined multiplier. The example shows the use of multiplication and addition primitives.

The division is a bit more complex case. Generally, the deployment of the division requires a much more complex logic circuit, and for this reason, we tend to avoid, where possible, the use of the division operator unless there are special cases.

If we have to divide by 2 or power of two, the implementation is simply shifting to the right of the number to divide.

In binary representation, shifting to the right of a position corresponds to a division for two, as in a decimal representation a shifting to the right corresponds to a division by 10.

## Fixed vs floating point representation

When we use FPGA, we need to deal with fixed-point arithmetic. Even if new FPGA like Intel Stratix 10 implements floating-point multiplier, if we need to implement Digital Signal Processing (DSP) in FPGA we have to use fixed-point arithmetic.

Many people have serious problems dealing with fixed-point binary representation or quantization of floating point value in fixed-point.

In this post, I explained how to divide a number for a constant in VHDL. Of course, you need to have the basic of binary number representation that you can find in this post.

## What is an array

In any software programming language, when we need to deal with a collection of elements of the same type we can take advantage of the dedicated data structures provided by the language. In VHDL such kind of structure is defined “array“.

We can collect any data type object in an array type, many of the predefined VHDL data types are defined as an array of a basic data type.

An example is:

type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;

## VHDL Iterative Statement

In VHDL the FOR-LOOP statement is a sequential statement that can be used inside a process statement as well as in subprograms.

The FOR-LOOP statement is used whenever an operation needs to be repeated.

In VHDL behavioral code, i.e. when we write a VHDL code of a test bench in a pure behavioral model, the FOR-LOOP usage statement can be considered as a common SW implementation of a loop statement as in the other SW languages.

In VHDL RTL the FOR-LOOP statement shall be used taking into account the final hardware implementation.

This consideration, of course, is always valid in any VHDL code implementation.

The FOR-LOOP statement is more difficult to visualize as a final result in HW implementation. Read More

## VHDL multiple conditional statement

In this post, we have introduced the conditional statement. The IF-THEN-ELSE is a VHDL statement that allows implementing a choice between different options. When the number of options greater than two we can use the VHDL “ELSIF” clause.  In case of multiple options, VHDL provides a more powerful statement both in the concurrent and sequential version:

• CASE-WHEN sequential statement
• WITH-SELECT concurrent statement

## VHDL Conditional Statement

VHDL is a Hardware Description Language that is used to describe at a high level of abstraction a digital circuit in an FPGA or ASIC.

When we need to perform a choice or selection between two or more choices, we can use the VHDL conditional statement.

Since the VHDL is a concurrent language, it provides two different solutions to implement a conditional statement:

• sequential conditional statement
• concurrent conditional statement

## Binary Counters vs BCD Counters

A counter is a common component in VHDL design. When we deal with FPGA, the most used counters are the binary counter.

These counters use the modulo-two arithmetic.
For example, of a 3-bit counter, the values that can be addressed are

then the counter wrap-around starting again from zero, as clear in Figure 1.

# Single-port and Dual-port RAM understanding

The internal FPGA memory macro usually implements a single-port or dual-port memory as in Figure 1.

Similar consideration can be done for ROM implementation. In this case, by definition, no write port is present so the distinction is between single-port and dual-port ROM. Read More

## How to Realize a FIR Test Bench in FPGA

### Debugging a FIR in FPGA

The VHDL, and other hardware description languages such as Verilog, SistemVerolog and so on, allows us to simulate your digital design in a very accurate way.

If you write a good VHDL code after the simulation you are very confident that your VHDL design will work as it should. When you go to silicon often there are problems and you should debug your VHDL code.

Here you can find some of the common issues you have during the test of VHDL design on FPGA. The modern FPGAs allows the user to enable debug facility inside the silicon using a proprietary debug tool very like embedded logic state analyzer.

Using Altera Quartus II you can enable the Signal Tap Analyzer or the equivalent using Xilinx Chipscope.

In this post, we are going to see an example on how to debug a FIR using the push button and the seven-segment display of a typical demo board with an FPGA, implementing a complete VHDL test bench that will be implemented in a Terasic DE0 board. Read More