In Digital Signal Processing, often is required the implementation of transcendental math function as trigonometric functions (sine, cosine, tan, atan) or exponential and logarithmic functions and so on. An efficient way, when possible, is to implement an approximation of these functions using Look Up Table or LUT as the sine example in Figure1.
Figure1 – LUT implementing sine function
In modern FPGA a large amount of RAM/ROM memory is available, so the LUT implementation requires only FPGA memory hardware resources and few additive registers. Read More
How To Implement Shift-Register in VHDL Using a FIFO
When you implement a digital design one of the most used building block is a pipeline or a digital delay line. For instance, you could need to compensate the delay between two
For instance, you could need to compensate the delay between two branches of a digital circuit in terms of clock cycle. In
In Figure1, there is a possible example where you have to subtract the value of an input sample of an ADC and this value is computed using the ADC sample as well. In the figure, the “Processing Block” compute the required functions over the current ADC samples. Then the correction has to be subtracted to the current ADC input samples. So you need to compensate the processing time in terms of clock cycle using a feed-forward architecture implemented as a delay line.
Figure1 – An example of digital delay line requirement
When you simulate a design in VHDL it is very useful to have the possibility to save some simulation results. For example, if you need to compare the simulation results with reference test vector, or simply to document the simulation in a test report.
Write File Test Bench Architecture
In VHDL, there are predefined libraries that allow the user to write to an output ASCII file in a simple way. The TextIO library is a standard library that provides all the procedure to read from or write to a file. Read More
When you need to simulate a design in VHDL it is very useful to have the possibility to read the stimuli to provide to your Design Under Test (DUT) reading from an input file.
This approach allows you to have different test bench input stimuli using the same VHDL test bench code.
Read from file in VHDL and generate test bench stimuli
In VHDL, there are predefined libraries that allow the user to read from an input ASCII file in a simple way. Read More
Which can be an effective and elegant way to describe a control logic? Which strategies would you use?
One possibility is trivial: start writing your control logic with a series of “if then else” or “case” statement.
Definitely, not an elegant method but in some ways could perhaps be efficient if you are particularly skilled at simplifying the description of your control logic.
Another possibility is to use a Finite State Machine (FSM). Read More
Before reading the post, if you need the VHDL code of the SPI controller, just put your email in the box you find in the post. There is no need to post a comment asking me for the code 🙂 If you don’t receive the email, please check your SPAM folder, enjoy!
The Serial Peripheral Interface (SPI) bus is a synchronous serial communication controller specification used for short-distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de-facto standard. Typical applications include sensors, Secure Digital cards, and liquid crystal displays.
SPI devices communicate in full-duplex mode using a master-slave architecture with a single master. The SPI master device originates from the frame for reading and writing. Multiple SPI slave devices are supported through selection with individual slave select (SS) lines as in Figure 2.
Finite Impulse Response (FIR) filters are characterized by a time response depending only on a given number of the last samples of the input signal. For a causal discrete-time FIR filter of order N, each value of the output sequence is a weighted sum of the most recent input values:
where:
x[n] is the input signal,
y[n] is the output signal,
N is the filter order; a Nth-order filter has (N+1) terms on the right-hand side
bi is the value of the impulse response at the i’th instant for 0<= i<=N of a Nth-order FIR filter. If the filter is a direct form FIR filter then is also a coefficient of the filter (see Figure1).
The ADC converters translate analog electrical signals, usually the voltage amplitude, into a sequence of discrete values (integer number) for data processing purposes. The bit resolution of the analog to digital conversion determines the magnitude of the quantization error. The number of discrete levels depends on the number of ADC bit resolution. For an N-bit ADC, the number of discrete possible values is 2^N.
For example, for 8-bit ADC the input signal is discretized in 2^8=256 different values.
Probably you will be asked, “Why should I learn VHDL?” If you are involved in Electronic Hardware design using FPGA or ASIC, you’ll definitely hear of the high-level compilers/synthesizer. Now certainly, you may be thinking:
“I’m really a lucky person because the current technology is helping me in designing FPGA or ASIC hardware without the need to learn all about that hardware”.
The question is: can I use High-level synthesizer to exploit the ability of the software to develop different projects? The answer is probably yes, but with some limitation. Think about this issue: if you need to call a guy to develop a project, who you would you trust?
Who improvise himself/herself hardware designer?
A person who deeply understands the problems of the system?
The high-level synthesizers have made more democratic access to the FPGA hardware development, but keeping away the designer from the physical device, away from the silicon implementation.
Although, on one hand, using high-level synthesizers the design can be developed very fast, on the other side there is the risk of not having control of what you are doing.
If you need a professional service, you want to be sure that the person you hired have the mastery of what he/she is doing.
When the going gets tough, the tough get going.
The VHDL is a Hardware Description Language that allows the designer to model the hardware circuit with maximum flexibility and relatively easily. Doing so, however, it requires that you also have the knowledge of what are you doing. Another powerful Hardware Description Language is Verilog.
Most often this type of languages are confused and mistakenly associated to a purely software language.
This is due to the fact that it is difficult to make clear the distinction between software programming language and hardware description language.
The VHDL is a language that is used to describe a hardware project with enough level of abstraction, but in the same time, with a complete control of the hardware model.
With VHDL you can translate high-level design description into logic gates inside the silicon. If we start from this principle you can better understand how to use this powerful tool.
Few days ago, Intel announced they want to acquire ALTERA, one of the biggest FPGA providers. Such fusion can pave the way toward a new era of microprocessors with embedded FPGA used as a custom and re-configurable co-processor.
The Intel sign is shown at Intel headquarters in Santa Clara.
It could be a new page in the use of such devices by opening the opportunity to the hardware designers to develop new projects on innovative platforms.
The knowledge of VHDL in this field becomes certainly a must.
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