How to implement a shift register in VHDL

January 20, 2019January 20, 2019 Surf-VHDL 2 Comments

I wrote many posts on different VHDL topics. Many of them deal with quite a complex concept.

Some days ago, I realized that I didn’t write anything “simple” dealing with the basic hardware building block.

I realized that since I received many email and telegram messages asking me to explain them some line of VHDL code. These lines are relative to a simple shift register implementation.

Sometimes what is simple for you, is not for other people!

In this post, I would like to propose three different ways of implementing a shift register in VHDL.

First of all, let’s review what is a shift register. It could be represented with a series of flip flop connected in series, where the output of one flip-flop is the input of the other.

In Figure 1 you can see a visual representation.

Figure 1 shift register architecture example

As stated before, there are at least three different ways to describe such hardware structure in VHDL. The three descriptions are totally equivalent.

How to implement a digital filter without multiplier

July 29, 2018August 4, 2018 Surf-VHDL 8 Comments

FIR filter overview

When we implement an FIR filter in FPGA or ASIC the major cost in terms of area resources derives from the multiplier units required for coefficient multiplication. Depending on the frequency response of the filter, the number of coefficients (or filter taps) could become large.

As clear from an FIR filter architecture in Figure 1 the number of multiplier operations is equal to the number of taps, for a long filter the area required will be demanding.

How to implement a Reed-Solomon Encoder in VHDL

July 25, 2018July 25, 2018 Surf-VHDL 5 Comments

What is an RS-Encoder

When you want to transfer information from a source to a target, you want to be sure that such information is transferred without errors.

When you transfer an information through a communication channel, such information will be prone to errors.

In order to minimize or eliminate the number of errors during the information transmission, we can adopt some error correction strategies.

Figure 1 – Satellite communication corrupted by the link channel noise

Such strategies are named FEC, i.e. Forward Error Correction. As you can imagine, nothing is for free. If you want to guarantee an error-free transmission you need to “pay” in terms of transmission bandwidth and transmitter/receiver complexity.

Any error correction strategy needs to transmit much more information than the minimum required, in order to allow the receiver to recognize if the received information is correct and, in case of error, provide to correct the errors.

Without entering in the error correction field theory, very complex and wide argument, here we want to address one possible error correction algorithm.

There are two main approaches to implement Error- Correction Coding:

Block Coding: the symbol stream is divided into a block and coded.
Convolution Coding: convolution operation is applied to the symbol stream.

How to implement Galois multiplier in VHDL

July 8, 2018July 8, 2018 Surf-VHDL 10 Comments

Why Galois field

The Galois fields are mainly used in cryptography and error correction algorithm.

If you never deal with Galois field, at the beginning the topic could seem very hard to understand. In this post we want to address the galois field theory from the practical application point of view.

We will review:

the Galois arithmetic notation, just to understand how to interpret the equation
add/sum operation in Galois field
multiplier in Galois field

the third point maybe is the most difficult to understand.

It might put noses out of joint after reading this post because I will not be very rigorous in the representation of the theory of the Galois fields. This post wishes to give you a practical implementation starting point for your VHDL design using Galois arithmetic.

I put a lot of references at the bottom of this post that will help you to go deeper in the Galois field theory if you are really interested in it.

How to interface a FPGA processor with VHDL peripheral

July 7, 2018July 8, 2018 Surf-VHDL Leave a comment

FPGA and Processor

The modern FPGAs implement microprocessor internally either as soft-processor or hard-processor. The soft-processor is intended as microprocessor implemented into the FPGA starting from a VHDL/Verilog code.

So, in this case, the processor is synthesized using the current FPGA technology (and layout tool).

Soft-processors have the advantages to be portable into a different technology. LEON processor is a soft-processor example that is realized as a stand-alone chip and can be integrated into a VHDL design as IP.

Figure 1 – FPGA-SoC Processor to peripheral interface

The Hard-processor is intended as a dedicated FPGA silicon area that implements the processor.

As you can understand, it is dependent on the FPGA are you using. For example, Intel Cyclone V SoC family implements a dual-core processor ARM-Cortex A9.

Another example is the Xilinx ZYNQ that implement different processor families, ARM-Cortex A9, Arm Cortex-A53.

When we use a processor in FPGA (hard-processor or soft-processor) sometimes we need to interface such processor with our custom peripheral implemented in VHDL (or Verilog or other custom implementation). In this case, we could experience different issues in the processor – peripheral interfacing:

A bus of different size
Different interface signals
Synchronization during READ/WRITE operation

How to implement an LFSR in VHDL

December 10, 2017December 10, 2017 Surf-VHDL 10 Comments

What is an LFSR

A linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. We can use this type of functions in many application such as counters, crypto, ber-meter, CRC generation, scrambling/descrambling algorithm, test application and so on

An LFSR of length N can generate 2^N-1 different states where the values look like pseudo-random values.

There are two different types of LFSR implementation the FIBONACCI and the GALOIS implementation as in Figure1. The LFSR implementations are equivalent.

If we are implementing the LFSR in hardware, the Galois implementation is much more efficient since use two input XOR function and the XOR function is implemented between two consecutive registers. Read More

How to implement a Multi Port memory on FPGA

June 2, 2017October 7, 2017 Surf-VHDL 2 Comments

Single-port and Dual-port RAM understanding

The internal FPGA memory macro usually implements a single-port or dual-port memory as in Figure 1.

In dual-port memory implementation, we should make the distinction between simple dual-port and true dual-port RAM. In a single-port RAM, the read and write operations share the same address at port A, and the data is read from output port A. In simple dual-port RAM mode, a dedicated address port is available for each read and write operation (one read port and one write port). A write operation uses write address from port A while read operation uses read address and output from port B. In true dual-port RAM mode, two address ports are available for reading or writing operation (two read/write ports). In this mode, you can write to or read from the address of port A or port B, and the data read is shown at the output port with respect to the read address port.

Figure 1 – difference between single port RAM, simple dual-port RAM, and true dual-port RAM

Similar consideration can be done for ROM implementation. In this case, by definition, no write port is present so the distinction is between single-port and dual-port ROM. Read More

How to compute the frequency of a clock

September 3, 2016October 7, 2017 Surf-VHDL 11 Comments

Clock and digital design

When you use an FPGA you always need a clock. When you start the debug of your VHDL layout code on FPGA, often your design doesn’t work as it should!

It’ the hardware my friend!

Digital design has a big advantage w.r.t analog design:

if you implement a (good) synchronous design and simulate it, you are very confident that the design can work as it should.

But the reality is different!

I have a bad news when you start to debug your design on FPGA it always doesn’t work… Did it happen to you?

There is also a good news… Read More

How to design a good Edge Detector

August 12, 2016December 17, 2018 Surf-VHDL 10 Comments

Level vs edge

In digital synchronous design sometimes we need to detect the transition ‘0’->’1′ or ‘1’->’0’ of a signal.

As a simple example, suppose you have a counter with enable input port connected to an external push button. You need to count +1 every time you push the button.

Figure1 – example of human generated pulse used to enable a counter

Let the counter clock to be for example 50 MHz. The clock period is 20 ns. Even if you are very very fast in pushing the button it will be difficult to generate a pulse of 20 ns in order to enable the counter for only one clock cycle.

For example, if you push the button even for few millisecond, let say for instance 200 ms, your counter will be enabled for 200 ms/20 ns = 10.000.000 of clock cycle!

As you can see we need another solution than trying to push the button very very fast! Read More

How to Implement a Programmable Timeout Counter

August 8, 2016October 7, 2017 Surf-VHDL Leave a comment

Control logic implementation

In this post, we want to implement a simple exercise in order to show how to implement a programmable time-out counter that uses three different input coding. It is an exercise in control logic that you can use in your FPGA/ASIC design.

The control logic is explained in Figure1:

Figure1 - Programmable Time-Out Counter Control logic — Figure1 – Programmable Time-Out Counter Control logic

we need to count three different type of events and the counting values can be programmable up to three different ways. For instance, starting with count 3 pulses from input 1 then 5 pulses from input 2 and then 7 pulses from input three. After that, the control logic shall generate a pulse. Read More