How to Implement a BCD Counter in VHDL

Binary Counters vs BCD Counters

A counter is a common component in VHDL design. When we deal with FPGA, the most used counter is the binary counter.

These counters use the modulo-two arithmetic.
For example, for a 3-bit counter, the values that can be addressed are

Figure 1 3-bit decimal counter behavior

then the counter wraps around starting again from zero, as shown in Figure 1.

In digital design we use base 2 arithmetic because all the logic and arithmetic is optimized for 2’complement representation.

Here you can find an example of binary number representation.

In our daily life, we process our math operations in base 10. A base 10 counter wraps around when it reaches value 9.

It is possible to emulate base 10 using a binary counter. This type of counter is named a BCD counter.

BCD stands for Binary Coded Decimal counter. Of course, a BCD counter is not optimized for base 2 arithmetic.

In hardware implementation such as FPGA or ASIC, this kind of counter requires additional logic gates to be implemented.

Why should we need a BCD counter?

There are some applications that can take advantage of BCD counter.
Setting aside the homework that can be assigned to a future young engineer, a possible application could be the implementation of a counter that displays the count result on a 7-segment display, without the need of binary-to-decimal conversion before the display.

In the past, the computer BIOS were implemented using BCD representation, ATARI consoles used BCD as well.

Implementing a BCD counter in VHDL

A BCD counter can be easily implemented with a 4-bit binary counter as shown in Figure 2 below

Figure 2 4-bit binary counter and BCD counter architecture

The BCD counter architecture can be represented using an unsigned binary accumulator that increments by 1, and a comparator.
When the counter reaches 9, the next count value will be 0, then the 4-bit counter wraps at 9 (“1001”), not at 15 (“1111”) as a 4-bit binary counter does.

A possible VHDL code of a BCD implementation is reported below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_counter1 is
port (
  i_clk                       : in  std_logic;
  i_rstb                      : in  std_logic;
  i_sync_reset                : in  std_logic;
  i_count_ena                 : in  std_logic;
  o_bcd                       : out std_logic_vector(3 downto 0));
end bcd_counter1;

architecture rtl of bcd_counter1 is
signal r_count                 : unsigned(3 downto 0);

begin

o_bcd  <= std_logic_vector(r_count);
p_count : process(i_clk,i_rstb)
begin
  if(i_rstb='0') then
    r_count      <= (others=> '0');
  elsif(rising_edge(i_clk)) then
    if(i_sync_reset='1') then
      r_count      <= (others=> '0');
    elsif(i_count_ena='1') then
      if(r_count = 9) then
        r_count      <= (others=> '0');
      else
        r_count      <= r_count + 1;
      end if;
    end if;
  end if;
end process p_count;

end rtl;

Figure 3 shows the simulation of the BCD counter

Figure 3 one digit BCD counter simulation

Four-digit BCD Counter

If we need to implement two or more digit BCD counter we need to handle the carry bit.

The carry is generated when the BCD counter reaches the value 9 and needs to count more. An example of four-digit BCD counter architecture is reported in Figure 4.

Figure 4 four-digit BCD counter architecture

Figure 5 shows the VHDL simulation of a four-digit BCD counter

Figure 5 4-digit BCD counter VHDL simulation

Conclusion

In this post, we implemented a BCD counter in VHDL.

One digit and 4-digit BCD counter architecture have been presented.

VHDL code for BCD counter can be copied and used in your VHDL design.

References

[1] https://en.wikipedia.org/wiki/Binary-coded_decimal

[2] https://en.wikipedia.org/wiki/Two%27s_complement

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