Hardware Design

Sometimes you need to perform a multiple data read from RAM in the same clock cycle. In this post, you will find the VHDL code implementing a Multi-Port RAM

Learn how to compute the frequency of a clock in FPGA using VHDL. Step-by-step guide with code, CDC synchronization, and an interactive simulator.

Learn how to design a reliable edge detector in VHDL, avoid common mistakes like the asynchronous trap, and handle metastability with a 2-register synchronizer.

Learn how to measure pulse duration inside an FPGA using VHDL. Build an edge detector and counters to measure HIGH and LOW phases without an oscilloscope.

Learn how to implement a programmable timeout counter in VHDL using a constant-based FSM approach. Includes complete VHDL code and interactive simulator.

Learn how to implement a programmable PWM in VHDL. Complete guide with VHDL code, simulation results, and interactive waveform visualizer for FPGA.

Learn how to interface a serial ADC to an FPGA using VHDL. Step-by-step guide to implement an SPI controller for the TI ADC128S022 on Altera DE0-nano.

Learn three VHDL methods to implement clock dividers: by two, by power of two, and by integer division. Includes VHDL code, simulation, and clock tree best practices.

Learn what a FIFO is, how circular buffers work with read/write pointers, and FPGA implementation tips including Gray code for clock domain crossing.