How to Implement Division in VHDL

November 26, 2017June 24, 2018 Surf-VHDL 12 Comments

VHDL integer division should be really avoided?

In VHDL there are the math primitive subtraction, addiction, and multiplication that are generally available in the libraries provided by the FPGA or ASIC vendor.

For example, in this post, we saw how to implement a pipelined multiplier. The example shows the use of multiplication and addition primitives.

The division is a bit more complex case. Generally, the deployment of the division requires a much more complex logic circuit, and for this reason, we tend to avoid, where possible, the use of the division operator unless there are special cases.

Figure 1 – division of two floating-point numbers

If we have to divide by 2 or power of two, the implementation is simply shifting to the right of the number to divide.

In binary representation, shifting to the right of a position corresponds to a division by two, as in a decimal representation a shifting to the right corresponds to a division by 10.

How to Quantize FIR Coefficient

November 13, 2017November 13, 2017 Surf-VHDL 3 Comments

Fixed vs floating point representation

When we use FPGA, we need to deal with fixed-point arithmetic. Even if new FPGA like Intel Stratix 10 implements floating-point multiplier, if we need to implement Digital Signal Processing (DSP) in FPGA we have to use fixed-point arithmetic.

Many people have serious problems dealing with fixed-point binary representation or quantization of floating point value in fixed-point.

Figure 1 – Floating-point vs Quantized FIR impulse response

In this post, I explained how to divide a number for a constant in VHDL. Of course, you need to have the basic of binary number representation that you can find in this post.

VHDL Array

November 5, 2017November 7, 2017 Surf-VHDL 12 Comments

What is an array

In any software programming language, when we need to deal with a collection of elements of the same type we can take advantage of the dedicated data structures provided by the language. In VHDL such kind of structure is defined “array“.

We can collect any data type object in an array type, many of the predefined VHDL data types are defined as an array of a basic data type.

An example is:

type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;

Figure 1 – example of VHDL array definition and addressing

VHDL FOR-LOOP statement

November 4, 2017September 20, 2020 Surf-VHDL 15 Comments

Before reading the post, if you need the VHDL code example of the FOR-LOOP, just put your email in the box you find in the post. There is no need to post a comment asking me for the code 🙂
If you don’t receive the email, please check your SPAM folder, enjoy!

VHDL Iterative Statement

In VHDL the FOR-LOOP statement is a sequential statement that can be used inside a process statement as well as in subprograms.

The FOR-LOOP statement is used whenever an operation needs to be repeated.

In VHDL behavioral code, i.e. when we write a VHDL code of a test bench in a pure behavioral model, the FOR-LOOP usage statement can be considered as a common SW implementation of a loop statement as in the other SW languages.

In VHDL RTL the FOR-LOOP statement shall be used taking into account the final hardware implementation.

This consideration, of course, is always valid in any VHDL code implementation.

The FOR-LOOP statement is more difficult to visualize as a final result in HW implementation. Read More

VHDL CASE statement

November 3, 2017November 5, 2017 Surf-VHDL 6 Comments

VHDL multiple conditional statement

In this post, we have introduced the conditional statement. The IF-THEN-ELSE is a VHDL statement that allows implementing a choice between different options. When the number of options greater than two we can use the VHDL “ELSIF” clause. In case of multiple options, VHDL provides a more powerful statement both in the concurrent and sequential version:

CASE-WHEN sequential statement
WITH-SELECT concurrent statement

Figure 1 – Multiple conditional statement visual representation

IF-THEN-ELSE statement in VHDL

November 2, 2017November 3, 2017 Surf-VHDL 1 Comment

VHDL Conditional Statement

VHDL is a Hardware Description Language that is used to describe at a high level of abstraction a digital circuit in an FPGA or ASIC.

When we need to perform a choice or selection between two or more choices, we can use the VHDL conditional statement.

Since the VHDL is a concurrent language, it provides two different solutions to implement a conditional statement:

sequential conditional statement
concurrent conditional statement

Figure 1 – Typical conditional statement representation

How to Implement a BCD Counter in VHDL

October 18, 2017November 11, 2017 Surf-VHDL 30 Comments

Binary Counters vs BCD Counters

A counter is a common component in VHDL design. When we deal with FPGA, the most used counters are the binary counter.

These counters use the modulo-two arithmetic.
For example, of a 3-bit counter, the values that can be addressed are

then the counter wrap-around starting again from zero, as clear in Figure 1.

How to implement a Multi Port memory on FPGA

June 2, 2017October 7, 2017 Surf-VHDL 2 Comments

Single-port and Dual-port RAM understanding

The internal FPGA memory macro usually implements a single-port or dual-port memory as in Figure 1.

In dual-port memory implementation, we should make the distinction between simple dual-port and true dual-port RAM. In a single-port RAM, the read and write operations share the same address at port A, and the data is read from output port A. In simple dual-port RAM mode, a dedicated address port is available for each read and write operation (one read port and one write port). A write operation uses write address from port A while read operation uses read address and output from port B. In true dual-port RAM mode, two address ports are available for reading or writing operation (two read/write ports). In this mode, you can write to or read from the address of port A or port B, and the data read is shown at the output port with respect to the read address port.

Figure 1 – difference between single port RAM, simple dual-port RAM, and true dual-port RAM

Similar consideration can be done for ROM implementation. In this case, by definition, no write port is present so the distinction is between single-port and dual-port ROM. Read More

How to Realize a FIR Test Bench in FPGA

April 25, 2017May 5, 2023 Surf-VHDL 4 Comments

Debugging an FIR in FPGA

The VHDL, and other hardware description languages such as Verilog, SistemVerolog and so on, allow us to simulate your digital design in a very accurate way.

If you write a good VHDL code after the simulation you are very confident that your VHDL design will work as it should. When you go to silicon often there are problems and you should debug your VHDL code.

Here you can find some of the common issues you have during the test of VHDL design on FPGA. The modern FPGAs allow the user to enable debug facility inside the silicon using a proprietary debug tool very like an embedded logic state analyzer.

Using Altera Quartus II you can enable the Signal Tap Analyzer or the equivalent using Xilinx Chipscope.

Figure 1 – FIR Test Bench using Terasic DE0 board

In this post, we are going to see an example of how to debug an FIR using the push button and the seven-segment display of a typical demo board with an FPGA, implementing a complete VHDL test bench that will be implemented in a Terasic DE0 board.

Compute exp(x) in FPGA using VHDL

March 15, 2017October 7, 2017 Surf-VHDL Leave a comment

Where the exponential functions are used?

The exponential functions are used mainly where non-linear behavior are present. An example of exp(x) is given in Figure 1. Since we are dealing with an exponential behavior, in the normal use of the function, the value of the exponent is range limited. For example, your algorithm could use 0<x<1, or -1<x<1 and so on. It is very unlikely you should deal with x in the entire real range when you implement a signal processing algorithm in FPGA.