How to Declare a Procedure in VHDL
Learn how to declare a procedure in VHDL with a practical BUS access simulation example for test benches.
VHDL Basics
How to Implement Division in VHDL
Generally, in VHDL we try to avoid division. Here you can find a simple and efficient solution to implement VHDL code in FPGA for the division algorithm.
VHDL Array
Learn how to declare and use arrays in VHDL. One-dimensional and multidimensional arrays, initialization, MUX, LUT, and DSP examples.
VHDL FOR-LOOP statement
Learn how to use the VHDL FOR-LOOP statement in RTL. See how the synthesizer unrolls loops into hardware and why the loop range must be static.
VHDL CASE statement
When we need to select multiple options, VHDL provides the two equivalent statements: CASE-WHEN sequential statement and WITH-SELECT concurrent statement
IF-THEN-ELSE statement in VHDL
Understand the VHDL IF-THEN-ELSE sequential statement and its concurrent equivalent WHEN-ELSE. Learn how conditional statements translate to MUX and comparator hardware.
How to Implement a BCD Counter in VHDL
Learn how to implement a BCD (Binary Coded Decimal) counter in VHDL. Includes 1-digit and 4-digit architectures with VHDL code and test bench.
Write to File in VHDL using TextIO Library
Learn how to use the VHDL TextIO library to write simulation results to ASCII files. Includes formatting, CSV output, and a complete process example.
Read from File in VHDL using TextIO Library
Learn how to read stimuli from an input file in VHDL using the TextIO library. Step-by-step guide to readline and read procedures for testbench design.