the concept is the same.
you can start from this architecture. If you need different architecture, please, post a possible architecture the community can help you

Thank you, i searching average filter in image processing, can you help me?

G_FIL_L is the average length so you should get the sum of the last 4 inputs divided by 4

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;

entity AvgFilter is
generic (
G_DATA_W :integer := 16;
G_FIL_L :integer := 4
);
port (
clk :in std_logic;
rst :in std_logic;
en :in std_logic;
iv_data :in std_logic_vector(G_DATA_W-1 downto 0);
ov_avg :out std_logic_vector(G_DATA_W-1 downto 0)
);
end entity;

architecture AvgFilter_rtl of AvgFilter is

— calculate number of bits needed to extend sum vector
function sumlog2(m :positive) return natural is
begin
for index in 1 to 30 loop
if (m <= 2**index) then
return(index);
end if;
end loop;
return(31);
end function;

signal en_reg :std_logic;

— array for storing samples
type t_arr_FilL_x_data is array (G_FIL_L-1 downto 0) of unsigned(G_DATA_W-1 downto 0);
signal a_samples :t_arr_FilL_x_data;

begin
reg: process(clk)

— to add G_FIL_L values is needed sumlog2(G_FIL_L) more bits for result
variable v_sum :unsigned(G_DATA_W+sumlog2(G_FIL_L)-1 downto 0);

begin
if rising_edge(clk) then
if rst = '1' then
en_reg <= '0';
a_samples (others => ‘0’));
v_sum := (others => ‘0’);
ov_avg ‘0’);
else
en_reg <= en;

a_samples(0) <= unsigned(iv_data);
for i in 1 to G_FIL_L-1 loop
a_samples(i) ‘0’);
if en_reg = ‘1’ then
for i in 0 to G_FIL_L-1 loop
v_sum := v_sum + resize(a_samples(i), v_sum’length);
end loop;
end if;

ov_avg <= std_logic_vector(v_sum(G_DATA_W+sumlog2(G_FIL_L)-1 downto sumlog2(G_FIL_L))); — divide by sumlog2(G_FIL_L)
end if;
end if;
end process;
end architecture;

and file dataIn.dat : 890B
0D00
0044
0048
B10E
8F1A
00A0
0A0A

But when I simulation it just only takes the top 6 values, and the average filter result is only divided by 4. can you help me explain
this one and how can i handle more than 6 values. Thanks you so much

this is an FIR with an impulse response all one

https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/

just replace the generic value with a number. The generic is a static value known at compile time. It is used to write a parametric code.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity moving_average is
generic (
G_NBIT : integer := 16);
port (
i_clk : in std_logic;
i_rstb : in std_logic;
i_sync_reset : in std_logic;
— input
i_data_ena : in std_logic;
i_data : in std_logic_vector(G_NBIT-1 downto 0);
coeff : in std_logic_vector(G_NBIT-1 downto 0);
— output
o_data_valid : out std_logic;
o_data : out std_logic_vector(G_NBIT-1 downto 0));
end moving_average;

architecture rtl of moving_average is

signal G_AVG_LEN_LOG : integer;
type t_moving_average is array (0 to 2**G_AVG_LEN_LOG-1) of signed(G_NBIT-1 downto 0);
signal p_moving_average : t_moving_average;
signal r_acc : signed(G_NBIT+G_AVG_LEN_LOG-1 downto 0); — average accumulator
signal r_data_valid : std_logic;

begin
o_data <= i_data when i_data_ena='0';
G_AVG_LEN_LOG <= to_integer(signed(coeff));
p_average : process(i_clk,i_rstb)
begin
if(i_rstb='0') then
r_acc ‘0’);
p_moving_average (others=>’0′));
r_data_valid <= '0';
o_data_valid <= '0';
o_data ‘0’);
elsif(rising_edge(i_clk)) then
r_data_valid <= i_data_ena;
o_data_valid <= r_data_valid;
if(i_sync_reset='1') then
r_acc ‘0’);
p_moving_average (others=>’0′));
elsif(i_data_ena=’1′) then
p_moving_average <= signed(i_data)&p_moving_average(0 to p_moving_average'length-2);
r_acc <= r_acc + signed(i_data)-p_moving_average(p_moving_average'length-1);
end if;
o_data <= std_logic_vector(r_acc(G_NBIT+G_AVG_LEN_LOG-1 downto G_AVG_LEN_LOG)); — divide by 2^G_AVG_LEN_LOG

end if;
end process p_average;
end rtl;