Comments on: How to Implement FIR Filter in VHDL https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/ The Easiest Way To Learn VHDL Thu, 09 Jun 2022 09:38:58 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: jai moondra https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-27833 Thu, 09 Jun 2022 09:38:58 +0000 http://surf-vhdl.com/?p=709#comment-27833 hello sir, i want to design IIR chebyshev filter 1 and implementation on FPGA,

]]> By: Jai Moondra https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-27832 Thu, 09 Jun 2022 09:32:42 +0000 http://surf-vhdl.com/?p=709#comment-27832 In reply to Surf-VHDL.

what is your email ID sir?

]]> By: Dinnesh Goudd Nerella https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-17699 Thu, 01 Jul 2021 12:56:50 +0000 http://surf-vhdl.com/?p=709#comment-17699 In reply to Surf-VHDL.

Please send me the test bench code sir

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-14155 Sun, 13 Dec 2020 14:09:37 +0000 http://surf-vhdl.com/?p=709#comment-14155 In reply to Jair.

a correlator is a special case of a FIR, so you can easily adapt this code

]]> By: Jair https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-14038 Thu, 03 Dec 2020 20:55:09 +0000 http://surf-vhdl.com/?p=709#comment-14038 I need to perform a correlation algorithm, can you help me?

can i use this code ?

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-12827 Thu, 03 Sep 2020 21:16:37 +0000 http://surf-vhdl.com/?p=709#comment-12827 In reply to draco.

could you be more clear?

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-12826 Thu, 03 Sep 2020 21:15:13 +0000 http://surf-vhdl.com/?p=709#comment-12826 In reply to draco.

what do you mean with “change the sampling frequency”?

]]> By: draco https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-12773 Mon, 31 Aug 2020 18:52:18 +0000 http://surf-vhdl.com/?p=709#comment-12773 In reply to Surf-VHDL.

i use float core to convert my standard IEEE 32 bit float input to fixed point and use this code bud I dont know how to change the sampling frequency

]]> By: draco https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-12772 Mon, 31 Aug 2020 18:14:27 +0000 http://surf-vhdl.com/?p=709#comment-12772 how we can add latch enable input in this code
for example we have 100 clock sample rate so every 100 clock , for one clock we have latch enable = 1
so i_data in every 100 clock latch and filter
please help meee

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/#comment-12759 Sat, 29 Aug 2020 20:34:58 +0000 http://surf-vhdl.com/?p=709#comment-12759 In reply to LN.

you have to divide the positive number by 127 and the negative by 128

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