Comments on: How To Implement Clock Divider in VHDL https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/ The Easiest Way To Learn VHDL Tue, 22 Jan 2019 18:07:27 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Surf-VHDL https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-10523 Tue, 22 Jan 2019 18:07:27 +0000 http://surf-vhdl.com/?p=1033#comment-10523 In reply to Abey.

thank you

]]> By: Abey https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-10519 Tue, 22 Jan 2019 15:02:23 +0000 http://surf-vhdl.com/?p=1033#comment-10519 Good tutorial.. I also found this https://www.maxybyte.com/p/counter-in-vhdl-with-debouncer.html helpful

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-8458 Sun, 22 Apr 2018 09:50:00 +0000 http://surf-vhdl.com/?p=1033#comment-8458 In reply to HT.

Thank You!

]]> By: https://www.udemy.com https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-4296 Wed, 28 Feb 2018 23:59:40 +0000 http://surf-vhdl.com/?p=1033#comment-4296 Good article. I aam dealing with some of these issus as well..

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-1788 Mon, 12 Jun 2017 09:39:12 +0000 http://surf-vhdl.com/?p=1033#comment-1788 In reply to HT.

Thank You for your feedback!

]]> By: HT https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-1786 Sat, 10 Jun 2017 16:48:14 +0000 http://surf-vhdl.com/?p=1033#comment-1786 Excellent article, nicely explained. Helped in building knowledge base.

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-238 Mon, 23 May 2016 20:24:34 +0000 http://surf-vhdl.com/?p=1033#comment-238 In reply to J.

Thanks for your feedback,
in the example above is clear that the output is coming from a flip-flop and the clock netlist is buffered as from the examples.

]]> By: J https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-237 Mon, 23 May 2016 06:59:23 +0000 http://surf-vhdl.com/?p=1033#comment-237 In reply to Surf-VHDL.

Functionality isn’t the issue, it’s skew and the possibility of glitches.

Your approach doesn’t control for either of these. If the circuit is simple, you may get close to the correct result. More than likely, the tool will place all the combinatorial logic before the registers, but you can’t be sure of that.

Now, you _can_ use this sort of approach properly in FPGA or ASIC, but you would want to make sure 1, that the output is really registered and it didn’t decide to make (say) a ripple carry counter, 2, that any sort of glitch is filtered by at at least one more set of flops and 3, constraints are added to make sure that the APR tools know what skew is acceptable.

There is a reason that dedicated clock buffer and more importantly clock gate cells exist.

]]> By: Santiago Palomino https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-206 Tue, 17 May 2016 06:14:09 +0000 http://surf-vhdl.com/?p=1033#comment-206 In reply to Marcos Hervas.

Hello Marcos,
Yes, we use clock enable signals to reduce the number of clock domains, simplify synchronisation, and simplify clock routing. I find clock enable signals more suitable and portable. The only drawback is that the design uses a higher clock frequency, but my experience is that normally I get better timing results, and normally I don’t have enough clock buffers to ensure that all the derived clocks will be routed using low jitter/skew clock networks. My company uses clock enable signals as a rule, as all the tools and devices seem to always handle them better.

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-clock-divider-vhdl/#comment-202 Sat, 14 May 2016 17:57:22 +0000 http://surf-vhdl.com/?p=1033#comment-202 In reply to Marcos Hervas.

Hi Marcos,
you can use a “discrete” clock divider without any problem.
In order to explain better and clarify that no issue are present using this approach, I updated the post inserting an example that demonstrates the functionality.

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