Comments on: How to Implement a Finite State Machine in VHDL https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/ The Easiest Way To Learn VHDL Thu, 03 Sep 2020 21:18:49 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-12828 Thu, 03 Sep 2020 21:18:49 +0000 http://surf-vhdl.com/?p=767#comment-12828 In reply to Mahmoud.

you can use Altera or Xilinx layout tool

]]> By: Mahmoud https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-12766 Sun, 30 Aug 2020 18:02:48 +0000 http://surf-vhdl.com/?p=767#comment-12766 my question is if there is a tool which can convert VHDL code to FSM
in details job of these tool analyse the VHDL code(compiler) and draw FSM diagram (CAD tool)

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-12752 Sat, 29 Aug 2020 18:06:46 +0000 http://surf-vhdl.com/?p=767#comment-12752 In reply to Mahmoud.

you have to read VHDL, understand it and then write the diagram 🙂
Generally, you have to write a diagram and then code the FSM.
Some synthesis tools perform the FSM extraction and provide the diagram, you can start from this

]]> By: Mahmoud https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-12720 Wed, 26 Aug 2020 19:46:48 +0000 http://surf-vhdl.com/?p=767#comment-12720 how to do the opposite way???
I mean converting VHDL code to FSM

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-10877 Sun, 29 Dec 2019 16:16:45 +0000 http://surf-vhdl.com/?p=767#comment-10877 In reply to nick.

I don’t understand the question, can you reword?

]]> By: nick https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-10710 Sat, 19 Oct 2019 07:46:32 +0000 http://surf-vhdl.com/?p=767#comment-10710 hi there, Im new to this. I understand there are inputs so how will the constraints be set in terms of input output?

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-10682 Thu, 05 Sep 2019 19:55:01 +0000 http://surf-vhdl.com/?p=767#comment-10682 In reply to Victor Andre Quinones.

send me an email

]]> By: Victor Andre Quinones https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-10680 Tue, 03 Sep 2019 15:50:30 +0000 http://surf-vhdl.com/?p=767#comment-10680 If you don’t mind can you share your testbench?

]]> By: Giriraj Pawar https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-10675 Thu, 08 Aug 2019 09:22:36 +0000 http://surf-vhdl.com/?p=767#comment-10675 In reply to Surf-VHDL.

will that be always going to be ‘1’

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-finite-state-machine-in-vhdl/#comment-10587 Sun, 07 Apr 2019 12:00:10 +0000 http://surf-vhdl.com/?p=767#comment-10587 In reply to Balbinati.

thank you for your feedback, I appreciate it a lot!
ciao

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