this code can be used only in a test-bench.
If you are acquiring data on a real board, you need to connect your board with an external PC (or arduino board) and store this data in a file.
Check my online courses. There are some example
Ciao

Thank you!

there are a lot of syntactic mistakes…
start from
https://surf-vhdl.teachable.com/

https://surf-vhdl.com/vhdl-syntax-web-course-surf-vhdl/

———————————————————————————-
— Company:
— Engineer:
—
— Create Date: 09/19/2019 03:56:37 PM
— Design Name:
— Module Name: inverter_w_tb – Behavioral
— Project Name:
— Target Devices:
— Tool Versions:
— Description:
—
— Dependencies:
—
— Revision:
— Revision 0.01 – File Created
— Additional Comments:
—
———————————————————————————-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;

— Uncomment the following library declaration if using
— arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;

— Uncomment the following library declaration if instantiating
— any Xilinx leaf cells in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity inverter_w_tb is
— Port ( );
end inverter_w_tb;

architecture Behavioral of inverter_w_tb is

type bitf is file of std_ulogic;
constant clk_period : time := 10 ns;
signal done : std_logic := ‘0’;
signal x_in : std_ulogic := ‘0’;
signal clk : std_ulogic := ‘0’;
signal x_out: std_ulogic;

component inverter is
port (
data_in : in std_ulogic;
clk : in std_ulogic;
data_out: out std_ulogic);
end component inverter;

begin
done x_in,
clk => clk,
data_out=> x_out);

clk_process: process
begin
for i in 0 to 8 loop
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end loop;
wait;
end process;

stim_process: process
begin
x_in<='1';
wait for clk_period;
x_in<='1';
wait for clk_period;
x_in<='0';
wait for clk_period;
x_in<='0';
wait for clk_period;
x_in<='0';
wait for clk_period;
x_in<='0';
wait for clk_period;
x_in<='1';
wait for clk_period;
x_in<='0';
wait;
end process;

write_process: process(clk)
file file_handler : bitf open write_mode is "output.bin";
variable row: line;
begin
if rising_edge(clk) then
write(row, x_out);
writeline(file_handler, row);
end process;

end Behavioral;

Thank you!!