Comments on: VHDL FOR-LOOP statement https://surf-vhdl.com/vhdl-for-loop-statement/ The Easiest Way To Learn VHDL Sun, 20 Sep 2020 10:01:10 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Surf-VHDL https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10673 Sun, 04 Aug 2019 09:39:39 +0000 http://surf-vhdl.com/?p=1558#comment-10673 In reply to Mueen.

BAT algorithm is quite complex.
You need to decompose the algorithm hierarchically.
Implement and simulate the single entities. Then integrate each block in a top level and…
good luck 🙂

]]> By: Mueen https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10671 Sat, 27 Jul 2019 19:10:12 +0000 http://surf-vhdl.com/?p=1558#comment-10671 Hi,

I would like to implement optimization algorithms in FPGA, how can I do it?

]]> By: Mueen https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10670 Fri, 26 Jul 2019 17:29:32 +0000 http://surf-vhdl.com/?p=1558#comment-10670 Hi

I need to implement the following paper
“FPGA based hardware implementation of Bat Algorithm”.
How can I do it?

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10651 Mon, 10 Jun 2019 20:53:43 +0000 http://surf-vhdl.com/?p=1558#comment-10651 In reply to EnthuMan.

The code gives you a lot of error because contains syntactic error 🙂
take a look here
https://surf-vhdl.com/vhdl-case-statement/

]]> By: EnthuMan https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10648 Wed, 05 Jun 2019 08:58:39 +0000 http://surf-vhdl.com/?p=1558#comment-10648 Hello,
I am trying to write a demultiplexer using the loop statement in ISE.

The traditional way:
…..
case sel_adrs is
when x”00″ <= demux_data <= input(0); –input(0) is array of slv and demux_data is slv
when x"01" <= demux_data demux_data <= input(i);
end loop demux_data;

The above gave a lot of errors. Please guide

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10504 Thu, 10 Jan 2019 21:05:45 +0000 http://surf-vhdl.com/?p=1558#comment-10504 In reply to Almudena.

it depends. Not all the VHDL you can write is synthesizable. The same considerations are valid the loop structure

]]> By: Almudena https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10502 Thu, 10 Jan 2019 15:10:11 +0000 http://surf-vhdl.com/?p=1558#comment-10502 Are they always loop structures synthesizable?

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10481 Tue, 11 Dec 2018 20:40:30 +0000 http://surf-vhdl.com/?p=1558#comment-10481 In reply to farhath.

you can start from my course
https://surf-vhdl.teachable.com

]]> By: farhath https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10479 Tue, 11 Dec 2018 10:00:36 +0000 http://surf-vhdl.com/?p=1558#comment-10479 iam from signal processing background,i was basically doing project based on FPGA and VHDL side ,i wanna learn VHDL language ,which is the best procedure to learn VHDL ,pls suggest

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-for-loop-statement/#comment-10461 Wed, 14 Nov 2018 21:27:15 +0000 http://surf-vhdl.com/?p=1558#comment-10461 In reply to sina.

vacc4(4) is the element 5 of the array, each element is composed by 11 bit type unsigned,
the same for vacc4(5), is the 6-th element of the array.
Remember that array starts from 0.

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