Comments on: VHDL Array https://surf-vhdl.com/vhdl-array/ The Easiest Way To Learn VHDL Sun, 08 May 2022 16:05:10 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Surf-VHDL https://surf-vhdl.com/vhdl-array/#comment-27493 Sun, 08 May 2022 16:05:10 +0000 http://surf-vhdl.com/?p=1577#comment-27493 In reply to abi.

the first type casting is “std_logic_vector” is related to m1 signal type
to_integer(unsigned(s1) is related to convert to integer the signal s1

]]> By: abi https://surf-vhdl.com/vhdl-array/#comment-25467 Fri, 11 Feb 2022 10:47:09 +0000 http://surf-vhdl.com/?p=1577#comment-25467 In the Implementation of a LUT using an array in VHDL, you have written
m1 <= std_logic_vector(to_unsigned(C_LUT1(to_integer(unsigned(s1))),4));
This statement I don't understand. Can you explain it more clearly?

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-array/#comment-11846 Sat, 18 Apr 2020 21:39:19 +0000 http://surf-vhdl.com/?p=1577#comment-11846 In reply to Antonio.

you are right, it is a typo, I’ll fix it
thank you

]]> By: Antonio https://surf-vhdl.com/vhdl-array/#comment-11716 Tue, 31 Mar 2020 15:18:33 +0000 http://surf-vhdl.com/?p=1577#comment-11716 In the first picture of the array example,
vector(2)<=42 is on the 4rd element with index 3.
Shouldn't it be 3rd element and index 2?

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-array/#comment-10681 Thu, 05 Sep 2019 19:54:41 +0000 http://surf-vhdl.com/?p=1577#comment-10681 In reply to Valentin.

you can use a single array and use the index (2*i) and (2*i+1)

]]> By: Valentin https://surf-vhdl.com/vhdl-array/#comment-10679 Mon, 02 Sep 2019 12:45:04 +0000 http://surf-vhdl.com/?p=1577#comment-10679 In reply to Surf-VHDL.

I have a 1D array. I need to get 2 arrays: 1st – indexes 0,2,4,…, 2nd – indexes 1,3,5,…

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-array/#comment-10559 Mon, 04 Mar 2019 18:46:42 +0000 http://surf-vhdl.com/?p=1577#comment-10559 In reply to You.

You can use a Cordic

]]> By: You https://surf-vhdl.com/vhdl-array/#comment-10558 Sun, 03 Mar 2019 07:44:22 +0000 http://surf-vhdl.com/?p=1577#comment-10558 Any hint on how to develop a square root synthesizable design?
Thanks,

]]> By: Surf-VHDL https://surf-vhdl.com/vhdl-array/#comment-10452 Thu, 01 Nov 2018 11:05:03 +0000 http://surf-vhdl.com/?p=1577#comment-10452 In reply to Dongfang.

You can use a package where define your input type. For instance:

type t_my_input_row is array(0 to 12) of std_logic_vector(7 downto 0);
type t_my_input is array(0 to 12) of t_my_input_row;

your input/output port could be

my_input : in t_my_input;

]]> By: Dongfang https://surf-vhdl.com/vhdl-array/#comment-10451 Tue, 30 Oct 2018 16:06:14 +0000 http://surf-vhdl.com/?p=1577#comment-10451 Hello,
Firstly thanks very much for your post and i found it very helpful.
My questions is my input is an array of 13X13 8 bit vector and i feel wrong to simply type 169 lines for my input.
Is there another way of easier definition in Entity regarding arrays as input or output?

Thanks in advance

Dongfang

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