Comments on: How to implement a Reed-Solomon Encoder in VHDL https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/ The Easiest Way To Learn VHDL Tue, 25 Jul 2023 14:52:33 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-35281 Tue, 25 Jul 2023 14:52:33 +0000 http://surf-vhdl.com/?p=1707#comment-35281 In reply to Rob.

it is the generator polynomial for RS(7,3)
https://it.mathworks.com/help/comm/ref/rsgenpoly.html

]]> By: Rob https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-35087 Wed, 12 Jul 2023 16:37:14 +0000 http://surf-vhdl.com/?p=1707#comment-35087 In reply to Surf-VHDL.

But what is the logic behind using 5,1,5,4 to create this constant array?

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-27494 Sun, 08 May 2022 16:08:14 +0000 http://surf-vhdl.com/?p=1707#comment-27494 In reply to Ichrak.

is simply a constant array
(5,1,5,4)
represented as std_logic_vector at C_M bits

]]> By: Ichrak https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-27235 Thu, 28 Apr 2022 15:12:00 +0000 http://surf-vhdl.com/?p=1707#comment-27235 So helpful !!
I’d like to ask you how did you choose the G_poly :
constant G_GPOLY : t_pipe_enc := (
conv_std_logic_vector(5,C_M),
conv_std_logic_vector(1,C_M),
conv_std_logic_vector(5,C_M),
conv_std_logic_vector(4,C_M)); Please??
I can’t understand the structure of this conversion nor the values “5,1,5,4” that you picked to generate this poly

]]> By: Dimitrios Dirdiris https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-16660 Sun, 09 May 2021 17:15:43 +0000 http://surf-vhdl.com/?p=1707#comment-16660 Great article! Is it possible to post the Testbenches as well? Thank you in advance

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