Comments on: How to design a good Edge Detector https://surf-vhdl.com/how-to-design-a-good-edge-detector/ The Easiest Way To Learn VHDL Tue, 25 Jul 2023 14:45:06 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Surf-VHDL https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-35280 Tue, 25 Jul 2023 14:45:06 +0000 http://surf-vhdl.com/?p=1169#comment-35280 In reply to Nathan Wineera.

it could be possible that the edge is not detected.
You should use a complete clock pulse (high-low) that is at least of the length of the pulse you want to detect. Better if the clock pulse is 1/2 of the pulse length i.e. 1/clock frequency is at least double the pulse width

]]> By: Nathan Wineera https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-34902 Tue, 06 Jun 2023 11:44:43 +0000 http://surf-vhdl.com/?p=1169#comment-34902 What if you want to detect narrow pulses less than half the clock period ?

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10879 Sun, 29 Dec 2019 16:23:32 +0000 http://surf-vhdl.com/?p=1169#comment-10879 In reply to BeoJr.

because such function trigger the instantiation of a flip-flop connecting the signal inside de function to che clock pin of the flip-flop.
In this example we need to “sample” an edge on an signal

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10847 Fri, 27 Dec 2019 17:18:41 +0000 http://surf-vhdl.com/?p=1169#comment-10847 In reply to Unknown12345.

the pulse duration is related to the clock duration

]]> By: Unknown12345 https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10716 Wed, 30 Oct 2019 14:16:40 +0000 http://surf-vhdl.com/?p=1169#comment-10716 “This implementation contains a big mistake.
Let see a simulation of this circuits. As you can see, if the edge of the input signal is very close to the internal clock edge the pulse generated is very short as shown in Figure5 and Figure6. Moreover, it is possible to lose the detection due to the internal physical delay of the circuit.”

Would you like to elaborate? What was the intended duration of the pulse generated? One clock of 1000ns without getting interfered of input clock and also the input button?

]]> By: BeoJr https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10704 Tue, 15 Oct 2019 11:10:27 +0000 http://surf-vhdl.com/?p=1169#comment-10704 Hi, I was just wondering, is there any reason why I can’t use the “rising_edge()” and “falling_edge()” functions instead?

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10577 Fri, 22 Mar 2019 21:54:00 +0000 http://surf-vhdl.com/?p=1169#comment-10577 In reply to Daniel.

I read the example there are some issues in the first example.
The example uses an XOR it could be reduced to an AND, NOT as in this canonical example

]]> By: Daniel https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10572 Thu, 21 Mar 2019 11:22:46 +0000 http://surf-vhdl.com/?p=1169#comment-10572 Thank you for the post, it was an interesting read! However, I’m a bit sceptical to the section “Typical mistake in edge detector implementation”. Either the input signal is asynchronous, in which case both circuits suffer from metastability issues, or the input signal is synchronous, in which case either of the two circuits are fine depending on the use case. The second design may be favorable if you know that the pulse will last long enough for your needs, since less hardware is required and since it decreases the latency of that path (which e.g. is the need here: https://stackoverflow.com/questions/17429280/vhdl-edge-detection). Meanwhile, the added register in the first circuit may be a possible solution if the pulse doesn’t last long enough. Am I right? I’m new to hardware design and would very much like to know your opinion on this.

]]> By: Surf-VHDL https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10487 Mon, 17 Dec 2018 20:13:50 +0000 http://surf-vhdl.com/?p=1169#comment-10487 In reply to Quark.

Hi, thank you for your feedback!
In the post, I do not use /Q because the code is RTL code.
As you can see “not r1_input” in the RTL code is definitely R1_input_inv.
Moreover, it can be view as /Q.
The post would report a possible VHDL/RTL implementation of an edge-detector.
If you write a structural VHDL code using a Flip-Flop component with a /Q output you can avoid the use if the inverter.

The mistake is not the use of the inverter,
but the missing of the first flip-flop as you can see in Figure 5 where the edge is not detected.
I hope I answered your doubts
Ciao

]]> By: Quark https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-10486 Sun, 16 Dec 2018 16:38:46 +0000 http://surf-vhdl.com/?p=1169#comment-10486 I appreciated your article as a beginner in vhdl, however I think it could have been made much clearer.
Two pedagogical mistakes:
– The vhdl code does not correspond strictly to the preceding diagram. When reading the code for the first time we cannot help wonder what is this reset doing there ?
It just disturbs our mind which is focused on the main issue of the post.
In addition having the same signal names than in the diagram would also help a lot.

– Later on you show us a typical mistake found on other sites. My first thouht is why the heck removing the inverter and using the /Q output should not work ?
I realized later that you also made another change: you removed the first register and apparently that is the (only ?) reason why the circuit does not work.
But at the end of the article we still do not know if having only removed the inverter and using /Q could have caused any problems !

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