just an example

Thank you for sharing knowledge.
I am just wondering how I’d like to develop a tachometer using the MachX03LF FPGA board and display the pulse rate on the display. I use a 12MHz clock and have to use a small frequency so I used clock register (22) details of the code as below. Any advice would be great thank you.

Cheers, Jack

library ieee;
use ieee.std_logic_1164.all; — use stand logic
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

–library MACHXO3;
–use MACHXO3.all;

entity testCC2510 is
port(clkin: in std_logic;
reset: in std_logic;
SW4: in std_logic;
LED: out std_logic_vector(7 downto 0);
com: out std_logic;
D2_out: out std_logic_vector(6 downto 0);
D1_out: out std_logic_vector(6 downto 0);
D0_out: out std_logic_vector(6 downto 0);
DP1_out: out std_logic;
DP2_out: out std_logic;
LED_out: out std_logic_vector(7 downto 0));

— define the pin connections
attribute loc:string;
attribute loc of clkin: signal is “C8”;
attribute loc of D0_out: signal is “R13,T14,T12,R11,T11,M11,N10”;
attribute loc of D1_out: signal is “R10,P10,T10,R9,T9,N9,M8”;
attribute loc of D2_out: signal is “M6,L8,T8,P8,R7,R8,T7”;
attribute loc of com: signal is “P7”;
attribute loc of reset: signal is “G2”;–was K1
attribute loc of SW4: signal is “N1”;
attribute loc of DP1_out: signal is “P9”;
attribute loc of DP2_out: signal is “P11”;
attribute loc of LED_out: signal is “F3,D3,G3,C2,F5,E3,B1,C1″;
end;
architecture arch_testCC2510 of testCC2510 is

component SevenSeg
port(LEDin: in integer;
SevSegout: out std_logic_vector);
end component;

signal clkreg : std_logic_vector(31 downto 0);
signal c_clk: std_logic;
signal dig2: std_logic_vector(6 downto 0):=”1111111”;
signal dig1: std_logic_vector(6 downto 0);
signal dig0: std_logic_vector(6 downto 0);
signal DP1: std_logic:=’1′;
signal DP2: std_logic:=’1′;
signal count0: integer range 0 to 9;
signal count1: integer range 0 to 9;
signal oscpin: std_logic;

begin

clk1:process(clkin)
begin
if (clkin’event and clkin = ‘1’) then
clkreg <= clkreg+X"00000001";
end if;

c_clk <= clkreg(22);
oscpin <= clkreg(15);

end process clk1;

lcdmod:process(oscpin)
begin
if (oscpin='1') then
D2_out<=dig2;
D1_out<=dig1;
D0_out<=dig0;
DP1_out<=DP1;
DP2_out<=DP2;
else
D2_out<= not dig2;
D1_out<= not dig1;
D0_out<= not dig0;
DP1_out<= not DP1;
DP2_out<= not DP2;
end if;
com<=oscpin;

end process;

DD0:SevenSeg port map(count0,dig0);
DD1:SevenSeg port map(count1,dig1);

p_counter: process
begin
wait until rising_edge(c_clk);

if (SW4='1') then

if ((count1=9) and (count0=9)) then
count1<=0;
count0<=0;
elsif(count0=9) then
count1<=count1+1;
count0<=0;
else
count0<=count0+1;
end if;

else

if((count1=0) and (count0=0)) then
count1<=9;
count0<=9;
elsif(count0=0) then
count1<=count1-1;
count0<=9;
else
count0<=count0-1;

end if;

end if;

if reset = '0' then

count0<=0;
count1<=0;

end if;

end process p_counter;

LED_out SevSegoutSevSegoutSevSegoutSevSegoutSevSegoutSevSegoutSevSegoutSevSegoutSevSegoutSevSegout<="0000100";
end case Lab0;
end process;
end SevenSeg_arch;

yes, just use 32 bit in the counter

// Description : This module measures the priod of the connected signal //
// : Reference clock is 125Mhz/8ns //
// //
// Calculation : osc_out[15] generates unexpected flag //
// : osc_out[14:0]/16 is the priod in ns //
// : accuracy is 0.0625ns //
// //
// instance template: //
// oscilloscope #(.EXP_VALUE (16’h008)) oscilloscope_ (.clk_ref_125(clk_eth_f4),.clk_in(clk_ila),.osc_out(scp_ila)); //
// //

`timescale 1ns/1ps

module oscilloscope
#(
parameter EXP_VALUE = 12’h057
)
(
input wire clk_ref_125 ,
input wire clk_in,
output logic [15:0] osc_out = 0 // o – muxed signature from different egress

);

// Signal declarations
logic [6:0] divided_clk = 0;
logic [14:0] count_nxt ;
logic [14:0] count_ff = 0;
logic [14:0] period ;

// divided the clock to 8×16=128 since 8ns reference and 16 bit decimal
always @ (posedge clk_in)
divided_clk <= divided_clk + 1;

// generate pulse from the divided_clk[6] after sync to clk_ref_125 TODO
assign measure_pulse =

// flops
always @ (posedge clk_ref_125) begin
osc_out[14:0] <= period;
count_ff <= count_nxt;
end

// count period and restart at pulse
always_comb begin

count_nxt = count_ff;
period = osc_out[14:0];

// store and restart
if (measure_pulse) begin // —-

// increment only if not overflowing
if (!(&count_nxt)) begin // —-

// generate the higher bit as a flag
if (EXP_VALUE == (period[14:4]+period[3])) begin // —-
else begin // —-

end // always

endmodule

thank you for your feedback!
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Cheers!

what do you mean?
Can you explain better?