Comments for Surf-VHDL https://surf-vhdl.com/ The Easiest Way To Learn VHDL Sat, 18 Nov 2023 10:09:45 +0000 hourly 1 https://wordpress.org/?v=6.5.2 Comment on Read from File in VHDL using TextIO Library by Surf-VHDL https://surf-vhdl.com/read-from-file-in-vhdl-using-textio-library/#comment-35893 Sat, 18 Nov 2023 10:09:45 +0000 http://surf-vhdl.com/?p=820#comment-35893 In reply to francis cagney.

Hi Francis,
the statement in the example should help to read from file and feed your synchronous design.
Of course, you can use different strategies. For instance use the “wait” statement into a process.
Regarding the formatting, VHDL is not so “smart” 🙂

]]> Comment on How to Implement a sinusoidal DDS in VHDL by Surf-VHDL https://surf-vhdl.com/how-to-implement-sinusoidal-dds-vhdl/#comment-35892 Sat, 18 Nov 2023 10:05:14 +0000 http://surf-vhdl.com/?p=1298#comment-35892 In reply to Mark Spring.

Hi Mark, thank you for pointing me out!
Now is ok.

]]> Comment on How to Connect a Serial ADC to an FPGA by Mathieu Winger https://surf-vhdl.com/how-to-connect-serial-adc-fpga/#comment-35820 Sat, 04 Nov 2023 21:12:38 +0000 http://surf-vhdl.com/?p=1077#comment-35820 Hello !
I am looking for some code that uses the ADC from the DE0-Nano board and that reads data from the 8 analog input channels by multiplexing. The langage could be Verilog or VHDL or even C code.
Any idea ?
Thanks in advance…
Mathieu Winger

]]> Comment on How to Implement a BCD Counter in VHDL by Eva https://surf-vhdl.com/how-to-implement-a-bcd-counter-in-vhdl/#comment-35648 Fri, 29 Sep 2023 16:38:31 +0000 http://surf-vhdl.com/?p=1496#comment-35648 I would like to get the 4 digit BCD counter,
Thank you

]]> Comment on How to Implement a sinusoidal DDS in VHDL by RANITA PAL https://surf-vhdl.com/how-to-implement-sinusoidal-dds-vhdl/#comment-35643 Tue, 26 Sep 2023 07:48:02 +0000 http://surf-vhdl.com/?p=1298#comment-35643 Can u please share the testbench with me too?

]]> Comment on How to Implement a sinusoidal DDS in VHDL by Mark Spring https://surf-vhdl.com/how-to-implement-sinusoidal-dds-vhdl/#comment-35597 Wed, 13 Sep 2023 21:42:00 +0000 http://surf-vhdl.com/?p=1298#comment-35597 In the section “Spur Magnitude due to the phase truncation,” it should be “12*6=72” (not “16*6=72”).

]]> Comment on Read from File in VHDL using TextIO Library by francis cagney https://surf-vhdl.com/read-from-file-in-vhdl-using-textio-library/#comment-35408 Sat, 12 Aug 2023 12:49:21 +0000 http://surf-vhdl.com/?p=820#comment-35408 You don’t actually need for it to be clocked. You can have a sequential process in the simulator with while loops and ifs. Unless you have an FPGA with a filing system the code above is only for the simulator.

Is there something like stdio in VHDL so you could report constants nicely formatted?
or use

variable buf: line;
lprintf(buf, “hello %d”, 10);
write(output, buf)

]]> Comment on How to implement a Reed-Solomon Encoder in VHDL by Surf-VHDL https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-35281 Tue, 25 Jul 2023 14:52:33 +0000 http://surf-vhdl.com/?p=1707#comment-35281 In reply to Rob.

it is the generator polynomial for RS(7,3)
https://it.mathworks.com/help/comm/ref/rsgenpoly.html

]]> Comment on How to design a good Edge Detector by Surf-VHDL https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comment-35280 Tue, 25 Jul 2023 14:45:06 +0000 http://surf-vhdl.com/?p=1169#comment-35280 In reply to Nathan Wineera.

it could be possible that the edge is not detected.
You should use a complete clock pulse (high-low) that is at least of the length of the pulse you want to detect. Better if the clock pulse is 1/2 of the pulse length i.e. 1/clock frequency is at least double the pulse width

]]> Comment on How to implement a Reed-Solomon Encoder in VHDL by Rob https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comment-35087 Wed, 12 Jul 2023 16:37:14 +0000 http://surf-vhdl.com/?p=1707#comment-35087 In reply to Surf-VHDL.

But what is the logic behind using 5,1,5,4 to create this constant array?

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