Hardware Structure Archives - Surf-VHDL https://surf-vhdl.com/category/hardware-structure/ The Easiest Way To Learn VHDL Sun, 20 Jan 2019 18:07:08 +0000 en-US hourly 1 https://wordpress.org/?v=6.6.2 https://surf-vhdl.com/wp/wp-content/uploads/2016/11/cropped-SURFVHDL_400x400-32x32.jpg Hardware Structure Archives - Surf-VHDL https://surf-vhdl.com/category/hardware-structure/ 32 32 How to implement a shift register in VHDL https://surf-vhdl.com/how-to-implement-a-shift-register-in-vhdl/ https://surf-vhdl.com/how-to-implement-a-shift-register-in-vhdl/#comments Sun, 20 Jan 2019 18:05:06 +0000 https://surf-vhdl.com/?p=1842 I wrote many posts on different VHDL topics. Many of them deal with quite a complex concept. Some days ago, I realized that I didn’t write anything “simple” dealing with the basic hardware building block. I realized that since I received many email and telegram messages asking me to explain them some line of VHDL […]

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]]> https://surf-vhdl.com/how-to-implement-a-shift-register-in-vhdl/feed/ 2 How to implement a digital filter without multiplier https://surf-vhdl.com/how-to-implement-a-digital-filter-without-multiplier/ https://surf-vhdl.com/how-to-implement-a-digital-filter-without-multiplier/#comments Sun, 29 Jul 2018 09:47:53 +0000 https://surf-vhdl.com/?p=1720 FIR filter overview When we implement an FIR filter in FPGA or ASIC the major cost in terms of area resources derives from the multiplier units required for coefficient multiplication. Depending on the frequency response of the filter, the number of coefficients (or filter taps) could become large. As clear from an FIR filter architecture […]

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]]> https://surf-vhdl.com/how-to-implement-a-digital-filter-without-multiplier/feed/ 8 How to implement a Reed-Solomon Encoder in VHDL https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/ https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/#comments Wed, 25 Jul 2018 18:16:12 +0000 http://surf-vhdl.com/?p=1707 What is an RS-Encoder   When you want to transfer information from a source to a target, you want to be sure that such information is transferred without errors. When you transfer an information through a communication channel, such information will be prone to errors. In order to minimize or eliminate the number of errors […]

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]]> https://surf-vhdl.com/how-to-implement-a-reed-solomon-encoder-in-vhdl/feed/ 6 How to implement Galois multiplier in VHDL https://surf-vhdl.com/how-to-implement-galois-multiplier-in-vhdl/ https://surf-vhdl.com/how-to-implement-galois-multiplier-in-vhdl/#comments Sun, 08 Jul 2018 17:46:20 +0000 http://surf-vhdl.com/?p=1695 Why Galois field The Galois fields are mainly used in cryptography and error correction algorithm. If you never deal with Galois field, at the beginning the topic could seem very hard to understand. In this post we want to address the galois field theory from the practical application point of view. We will review: the […]

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]]> https://surf-vhdl.com/how-to-implement-galois-multiplier-in-vhdl/feed/ 10 How to interface a FPGA processor with VHDL peripheral https://surf-vhdl.com/how-to-interface-a-fpga-processor-with-vhdl-peripheral/ https://surf-vhdl.com/how-to-interface-a-fpga-processor-with-vhdl-peripheral/#respond Sat, 07 Jul 2018 17:33:02 +0000 http://surf-vhdl.com/?p=1680 FPGA and Processor The modern FPGAs implement microprocessor internally either as soft-processor or hard-processor. The soft-processor is intended as microprocessor implemented into the FPGA starting from a VHDL/Verilog code. So, in this case, the processor is synthesized using the current FPGA technology (and layout tool). Soft-processors have the advantages to be portable into a different […]

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]]> https://surf-vhdl.com/how-to-interface-a-fpga-processor-with-vhdl-peripheral/feed/ 0 How to implement an LFSR in VHDL https://surf-vhdl.com/how-to-implement-an-lfsr-in-vhdl/ https://surf-vhdl.com/how-to-implement-an-lfsr-in-vhdl/#comments Sun, 10 Dec 2017 13:45:02 +0000 http://surf-vhdl.com/?p=1615 What is an LFSR A linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. We can use this type of functions in many application such as counters, crypto, ber-meter, CRC generation, scrambling/descrambling algorithm, test application and so on An LFSR of length N can generate […]

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]]> https://surf-vhdl.com/how-to-implement-an-lfsr-in-vhdl/feed/ 12 How to implement a Multi Port memory on FPGA https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/ https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/#comments Fri, 02 Jun 2017 21:08:17 +0000 http://surf-vhdl.com/?p=1451 Single-port and Dual-port RAM understanding The internal FPGA memory macro usually implements a single-port or dual-port memory as in Figure 1. In dual-port memory implementation, we should make the distinction between simple dual-port and true dual-port RAM. In a single-port RAM, the read and write operations share the same address at port A, and the […]

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]]> https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/feed/ 2 How to compute the frequency of a clock https://surf-vhdl.com/compute-frequency-clock/ https://surf-vhdl.com/compute-frequency-clock/#comments Sat, 03 Sep 2016 14:03:33 +0000 http://surf-vhdl.com/?p=1156 Clock and digital design When you use an FPGA you always need a clock. When you start the debug of your VHDL layout code on FPGA, often your design doesn’t work as it should! It’ the hardware my friend! Digital design has a big advantage w.r.t analog design: if you implement a (good) synchronous design and […]

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]]> https://surf-vhdl.com/compute-frequency-clock/feed/ 11 How to design a good Edge Detector https://surf-vhdl.com/how-to-design-a-good-edge-detector/ https://surf-vhdl.com/how-to-design-a-good-edge-detector/#comments Fri, 12 Aug 2016 08:04:41 +0000 http://surf-vhdl.com/?p=1169 Level vs edge In digital synchronous design sometimes we need to detect the transition ‘0’->’1′ or ‘1’->’0’ of a signal. As a simple example, suppose you have a counter with enable input port connected to an external push button. You need to count +1 every time you push the button. Let the counter clock to be […]

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]]> https://surf-vhdl.com/how-to-design-a-good-edge-detector/feed/ 10 How to Implement a Programmable Timeout Counter https://surf-vhdl.com/how-to-implement-a-programmable-timeout-counter/ https://surf-vhdl.com/how-to-implement-a-programmable-timeout-counter/#respond Mon, 08 Aug 2016 13:23:34 +0000 http://surf-vhdl.com/?p=1132 Control logic implementation In this post, we want to implement a simple exercise in order to show how to implement a programmable time-out counter that uses three different input coding. It is an exercise in control logic that you can use in your FPGA/ASIC design. The control logic is explained in Figure1: we need to […]

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