In the previous page, we have introduced the VHDL entity construct that provides a method to abstract the functionality of a circuit description to a higher level.
An entity always has one or more architectures that provide describing the behavior of circuit.
Using VHDL we can translate the same behavior in several different implementations.
Behavioral Coding Style
Is the highest level of abstraction provided by VHDL. An entity can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Design at this level is very similar to programming language (C++ or Visual Basic). This coding stile is typical of test benches.
Sequential / Data Flow Coding Style
At this level the entity is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design. The coding stile is called RTL: Register Transfer Logic. VHDL-RTL modeling is quite technology independent description. An efficient RTL design can be ported on different technology (ASIC or FPGA) without or with a little code modification.
Structural Coding Style
At this level the entity is implemented in terms of logic gates depending on chosen technology. Design at this level is similar to describing a design in terms of gate-level logic diagram. It is strongly technology dependent. The VHDL code is not portable on different technology. Generally, this approach is adopted when strong optimization is needed in order to achieve challenging constraint in terms of timing and sometimes area.
It is very similar to an assembly language.
In VHDL hardware design coding is possible, of course, to use any combination of the previous design styles. This case is generally called hybrid style model.
The next section will address the structural modeling and the hierarchical approach.