Binary Counters vs BCD Counters
A counter is a common component in VHDL design. When we deal with FPGA, the most used counters are the binary counter.
These counters use the modulo-two arithmetic.
For example, of a 3-bit counter, the values that can be addressed are
then the counter wrap-around starting again from zero, as clear in Figure 1.
In dealing with the digital design we use base 2 arithmetic because all the logic and arithmetic is optimized for 2’complement representation.
Here you can find an example of binary number representation.
In our daily life, we use to process our math operation in base 10. A base 10 counter wrap-around when reach value 9.
There is the possibility to emulate a base 10 using a binary counter. Such type of counters is named BCD counter.
BCD state for Binary Coded Decimal counter. Of course, a BCD counter is not optimized for base 2 arithmetic.
In hardware implementation such as FPGA or ASIC, this kind of counters requests an additional logic gate to be implemented.
Why should we need a BCD counter?
There are some applications that can take advantage of BCD counter.
Taking aside the homework that can be assigned to a future young engineer, a possible application could be the implementation of a counter that displays the count result on a 7-segment display, without the need of binary-to-decimal conversion before the display.
In the past, the computer BIOS were implemented using BCD representation, ATARI consoles used BCD as well.
Implementing a BCD counter in VHDL
A BCD counter can be easily implemented with a 4-bit binary counter as in the Figure2 below
The BCD counter architecture can be represented using an unsigned binary accumulator that increment by 1, and a comparator.
When the counter reaches 9, next count value will be 0, then the 4-bit counter wraps at 9 (“1001”), not at 15 (“1111”) as a 4-bin binary counter does.
A possible VHDL code of a BCD implementation is reported below:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity bcd_counter1 is port ( i_clk : in std_logic; i_rstb : in std_logic; i_sync_reset : in std_logic; i_count_ena : in std_logic; o_bcd : out std_logic_vector(3 downto 0)); end bcd_counter1; architecture rtl of bcd_counter1 is signal r_count : unsigned(3 downto 0); begin o_bcd <= std_logic_vector(r_count); p_count : process(i_clk,i_rstb) begin if(i_rstb='0') then r_count <= (others=> '0'); elsif(rising_edge(i_clk)) then if(i_sync_reset='1') then r_count <= (others=> '0'); elsif(i_count_ena='1') then if(r_count = 9) then r_count <= (others=> '0'); else r_count <= r_count + 1; end if; end if; end if; end process p_count; end rtl;
Figure3 is reported the simulation of the BCD counter
Four-digit BCD Counter
If we need to implement two or more digit BCD counter we need to handle the carry bit.
The carry is generated when the BCD counter reaches the value 9 and need to count more. An example of four-digit BCD counter architecture is reported in Figure4.
Figure5 shows the VHDL simulation of a four-digit BCD counter
If you want to receive the VHDL code of a 4-digit BCD counter with the complete VHDL test bench just put your email just below.
In this post, we implemented a BCD counter in VHDL.
One digit and 4-digit BCD counter architecture have been presented.
VHDL code for BCD counter can be copied and used in your VHDL design.
If you appreciated this post, please help us to share it with your friend.
If you need to contact us, please write to: firstname.lastname@example.org
We appreciate any of your comment, please post below: