How to Implement a Programmable Timeout Counter

Control logic implementation

In this post, we want to implement a simple exercise in order to show how to implement a programmable time-out counter that uses three different input coding. It is an exercise in control logic that you can use in your FPGA/ASIC design.

The control logic is explained in Figure1:

Figure1 - Programmable Time-Out Counter Control logic
Figure1 – Programmable Time-Out Counter Control logic

we need to count three different type of events and the counting values can be programmable up to three different ways. For instance, starting with count 3 pulses from input 1 then 5 pulses from input 2 and then 7 pulses from input three. After that, the control logic shall generate a pulse. (more…)

How to Connect a Serial ADC to an FPGA

Connection of Serial ADC to FPGA

The ADC (Analog to Digital Converter) can be interfaced to FPGA/ASIC in a different way depending on the output interface. This post gives an overview on the different interfaces available in ADC interfacing. On modern ADC, when the sampling rate is below the 10 Msample/sec the ADCs often implement a serial interface to provides sampled data to the user. The serial interface is little bit complex w.r.t. a parallel interface but the use of serial protocol reduces the number of wires and allows interfacing the ADC to a microprocessor like Arduino or Rapsberry Pi.

In the serial interface, the serial clock provided by the device connected to the ADC is used also as ADC sampling clock.

Figure1 - Serial ADC connected to FPGA
Figure1 – Serial ADC connected to FPGA

In this post, we will see an example of how to interface the TI ADC128S022 used in the Altera DE0-nano Board (more…)

How To Implement Clock Divider in VHDL

Clock Design Overview

Often, inside our FPGA design, we have the necessity to generate a local clock from the system clock. With system clock, I mean the clock that is coming from an external board oscillator. Many modern FPGAs have the possibility to generate internal clocks, different from the external clocks, using internal PLL hard macro. So you can generate internal FPGA clock as multiple or sub-multiple of the external system clock.

 

Figure1 - FPGA with internal clock divider
Figure1 – FPGA with internal clock divider

Sometimes the PLL are used to modify the clock phase or to generate different clocks at the same frequency with different phase relationship. For instance, 3 clocks:

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What is a FIFO?

Basic notion on FIFO (First-In First-Out)

FIFO means First-In First-Out. A FIFO is a structure used in hardware or software application when you need to buffer a data.
Basically, you can think about a FIFO as a bus queue in London.
The people that arrive first is the one who catch the bus first….

FIFO example at bus Stop
Figure1 – FIFO example at bus Stop

Of course, this example is valid only in London or in Japan, in other countries, it could be not be used 🙂 (more…)

How to Implement a Digital Delay Using a Dual Port Ram

Implement a Digital Delay Using a Dual Port Ram

The digital delay lines are one of the most used blocks in the digital design. When the digital delay is small in terms of numbers of Flip-Flop a simple shift register approach can be used. If the number of bits to delay i.e. the number of Flip-Flop utilized became important, a different approach should be used.

Digital Delay Implementation Architecture as Circular Buffer
Figure 1 – Digital Delay Implementation Architecture as Circular Buffer 

In this post, a FIFO delay approach has been presented. In that case, we used the FIFO macro provided by the FPGA vendor in order to implement a digital delay line.

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How To Generate Sine Samples in VHDL

In Digital Signal Processing, often is required the implementation of transcendental math function as trigonometric functions (sine, cosine, tan, atan) or exponential and logarithmic functions and so on. An efficient way, when possible, is to implement an approximation of these functions using Look Up Table or LUT as the sine example in Figure1.

Figure1 - LUT implementing sine function
Figure1 – LUT implementing sine function

 

In modern FPGA a large amount of RAM/ROM memory is available, so the LUT implementation requires only FPGA memory hardware resources and few additive registers. (more…)

How To Implement Shift-Register in VHDL Using a FIFO

How To Implement Shift-Register in VHDL Using a FIFO

When you implement a digital design one of the most used building block is a pipeline or a digital delay line. For instance, you could need to compensate the delay between two

For instance, you could need to compensate the delay between two branches of  a digital circuit in terms of clock cycle. In

In Figure1, there is a possible example where you have to subtract the value of an input sample of an ADC and this value is computed using the ADC sample as well. In the figure, the “Processing Block” compute the required functions over the current ADC samples. Then the correction has to be subtracted to the current ADC input samples. So you need to compensate the processing time in terms of clock cycle using a feed-forward architecture implemented as a delay line.

Figure1 – An example of digital delay line requirement

 

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Write to File in VHDL using TextIO Library

Write to File in VHDL using TextIO Library

When you simulate a design in VHDL it is very useful to have the possibility to save some simulation results. For example, if you need to compare the simulation results with reference test vector, or simply to document the simulation in a test report.

Write File Test Bench Architecture
Write File Test Bench Architecture

In VHDL, there are predefined libraries that allow the user to write to an output ASCII file in a simple way. The TextIO library is a standard library that provides all the procedure to read from or write to a file. (more…)

Read from File in VHDL using TextIO Library

Read from File in VHDL using TextIO Library

When you need to simulate a design in VHDL it is very useful to have the possibility to read the stimuli to provide to your Design Under Test (DUT) reading from an input file.

This approach allows you to have different test bench input stimuli using the same VHDL test bench code.

Read from file in VHDL and generate test bench stimuli
Read from file in VHDL and generate test bench stimuli

In VHDL, there are predefined libraries that allow the user to read from an input ASCII file in a simple way. (more…)