Website supports FPGA/ASIC junior and, why not, senior hardware designers in finding examples and useful hints for their VHDL designs.
Our target is to enable you to “surf” the VHDL: we made the VHDL learning experience as simple as it can be.
We are sharing with you everything that actually helped ourselves in mastering the VHDL.
The website contains many examples, explaining “how to” prepare the most common VHDL constructs, together with one section listing the “common mistakes” in VHDL design.
We strongly believe in knowledge sharing as one of the most important means to improve this world.
We would very much appreciate your cooperation either by submitting your questions or by sharing the link to this website with friends and colleagues
Enjoy the experience !